Hybrid PGNET-RTL Verification for Semiconductor Power Blocks
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Solution Overview
Problem
The increasing integration and shortened life cycles of semiconductor devices require accurate, efficient, and fast verification of power-related functions and characteristics, particularly in the connection of power wiring and operation of power switches, which existing methods struggle to address effectively.
Innovation Solution
A hybrid simulation environment is created by combining a power-gating netlist (PGNET) simulation environment for target blocks with a register transfer level (RTL) simulation environment for non-target blocks, allowing for efficient verification of power-related functions and characteristics in semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a full power-gating netlist (PGNET) simulation environment is used for all blocks, then verification accuracy of power-related functions is improved, but simulation time and computational complexity increase significantly
Solution Approach 1:
The patent applies local quality by creating different simulation environments for different blocks: target blocks use the accurate PGNET simulation environment with power wiring information, while non-target blocks use the simpler RTL simulation environment. This allows verification accuracy to be concentrated where needed (power-related blocks) while maintaining overall efficiency.
Solution Approach 2:
The patent segments the semiconductor device into target blocks and non-target blocks, and correspondingly segments the simulation environment into PGNET and RTL components. This segmentation enables selective application of detailed power simulation only to blocks where power verification is critical, resolving the contradiction between comprehensive verification and simulation time.
2Reliability
If detailed power wiring information and power-related characteristics are verified for all blocks, then verification completeness is improved, but verification efficiency and speed deteriorate
Solution Approach 1:
The patent implements local quality by applying detailed power verification (PGNET) only to target blocks where power-related functions need comprehensive checking, while using standard RTL verification for non-target blocks. This ensures verification completeness for power-critical areas without sacrificing overall verification efficiency.
Solution Approach 2:
The patent applies partial action by performing detailed power verification on only a subset of blocks (target blocks) rather than all blocks. This partial verification approach maintains reliability for power-related functions while significantly improving verification efficiency by avoiding redundant detailed checks in blocks where they are not critical.
3Ease of operation
If a unified simulation environment is used for all blocks, then ease of operation is improved, but adaptability to different verification needs deteriorates
Solution Approach 1:
The patent introduces dynamics by making the simulation environment adaptable and configurable. The verification system can dynamically select between PGNET and RTL environments for different blocks based on verification needs. This dynamic approach maintains ease of operation through automated environment selection while achieving high adaptability to different verification requirements.
Solution Approach 2:
The patent achieves universality by creating a hybrid verification system that can handle both detailed power verification (PGNET) and standard functional verification (RTL) within a single framework. This multi-functional system maintains operational simplicity while adapting to diverse verification needs across different blocks.
Data Source
AI summary
In a method of verifying a semiconductor device, input data defining the semiconductor device including a plurality of blocks is received. A first simulation environment is generated for a top module and at least one target block of the plurality of blocks in the top module. The first simulation environment includes power wiring information and additional power-related information. The top module represents an entire structure of the semiconductor device. A second simulation environment is generated for non-target blocks of the plurality of blocks other than the at least one target block. The second simulation environment is different from the first simulation environment. A verification operation is performed on the semiconductor device based on a hybrid simulation environment in which the first simulation environment and the second simulation environment are combined.