Hybrid Phase Change Memory with Bipolar-Unipolar Mode Switching
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Solution Overview
Problem
Traditional unipolar phase change memory devices are prone to data loss at high temperatures due to annealing of the amorphous state, while bipolar operation mode provides temperature immunity but at the cost of larger array size, complex bias circuits, and slower operation speed.
Innovation Solution
A memory device with a hybrid design that includes both bipolar and unipolar operation modes within the same memory array, using separate bias circuits for each mode, allowing for reliable data retention and high operation speed without increasing manufacturing costs or array size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If unipolar operation mode is used, then operation speed and cycling endurance are improved, but data retention at high temperature deteriorates
Solution Approach 1:
The patent changes the electrical parameters (polarity and magnitude) of the addressing circuit to enable dual-mode operation. By adjusting the voltage polarity and current direction, the same memory cell can operate in unipolar mode for fast writing or bipolar mode for temperature immunity, thus resolving the contradiction between speed and reliability
Solution Approach 2:
The patent introduces dynamic switching capability between unipolar and bipolar operation modes. The addressing circuit can dynamically adjust its configuration based on the required operation, allowing the system to optimize between speed and reliability depending on the specific task at hand
2Reliability
If bipolar operation mode is used, then temperature immunity is improved, but array size and device complexity increase
Solution Approach 1:
The patent makes the addressing circuit universal by enabling it to perform both unipolar and bipolar operations. The same circuit infrastructure supports multiple operation modes, eliminating the need for separate dedicated circuits for each mode and thereby reducing overall device complexity while maintaining temperature immunity capabilities
Solution Approach 2:
The patent merges the unipolar and bipolar operation capabilities into a single integrated addressing circuit. By combining the functionality of both operation modes into one circuit design, the patent reduces the overall complexity that would otherwise result from having separate circuits for each mode
3Reliability
If bipolar operation mode is used, then temperature immunity is improved, but operation speed deteriorates
Solution Approach 1:
The patent introduces dynamic switching capability between unipolar and bipolar operation modes. The addressing circuit can dynamically adjust its configuration based on the required operation, allowing the system to optimize between speed and reliability depending on the specific task at hand
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The hybrid design achieves temperature immunity, high memory capacity, fast operation speed, and reliable data retention while maintaining a compact size, as it leverages the reliability of bipolar mode and efficiency of unipolar mode simultaneously.
Implementation Method 1
The waveform WF1 forms the process of high current and rapid falling, which causes an amorphous phase change for the memory material 1013. The amorphous phase change will result in a high-R state of the memory material 1013.
Implementation Method 2
The waveform WF2 forms the process of low current and slow falling, which causes a crystalline phase change for the memory material 1013. The crystalline phase change will result in a low-R state of the memory material 1013.
Implementation Method 3
when it is exposed to high temperature, the amorphous state of the memory cell 101 can be annealed, which causes the material to transform from an amorphous phase into a crystalline phase of the low-R state.
Data Source
AI summary
A memory device is provided. The memory device includes a memory array; a first circuit electrically connected to the memory array, and causing the memory array to be operated in a first mode; and a second circuit electrically connected to the memory array, and causing the memory array to be operated in a second mode.