Hybrid Phase Interpolator Without Quadrature Clock Generation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing phase interpolators require differential quadrature phased clocks, which are not always available and result in coarse and inaccurate clock adjustments, with significant power consumption and variation over process, voltage, and temperature changes.
Innovation Solution
A hybrid phase interpolator using digital to analog converters and current mirrors to generate phase-adjusted clock signals from a single input signal and its inverted version, allowing for fine resolution and reduced power consumption without requiring quadrature clocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If traditional phase interpolators use differential quadrature phased clocks, then phase interpolation can be achieved, but device complexity and power consumption increase
Solution Approach 1:
The patent extracts and eliminates the requirement for quadrature clocks from the phase interpolator system. By using only a single clock signal and its inverted version instead of requiring four quadrature clocks, the design removes the complex clock generation infrastructure while maintaining phase interpolation functionality through current mirror-based switching.
Solution Approach 2:
The phase interpolator achieves multiple functions using minimal inputs. A single clock signal and its inverted version serve multiple purposes: they drive both current mirrors, enable phase interpolation across multiple phases, and eliminate the need for separate quadrature clock generation circuits, thereby reducing overall system complexity.
2Ease of manufacture
If LC delays or variable capacitors are used for clock delay, then implementation is simple, but delay resolution becomes coarse and inaccurate
Solution Approach 1:
The patent replaces physical/time-based delay mechanisms (LC delays, variable capacitors) with a current-based switching mechanism. By using current mirrors controlled by digital codes to switch between clock phases, the system achieves fine delay resolution through digital control rather than analog time constants, eliminating the coarse resolution limitation.
3Measurement precision
If stage blending with analog phase mixer is used, then fine resolution delay is achieved, but power consumption increases significantly
Solution Approach 1:
The current mirrors naturally switch states based on the clock signal and control codes without requiring additional power-hungry analog mixing circuits. The differential current switching mechanism inherently provides the phase blending function that traditional analog mixers perform, but with significantly lower power consumption by leveraging the existing clock signal energy.
4Measurement precision
If traditional phase interpolators are used, then fine delay resolution is achieved, but variation over process, voltage, and temperature increases
Solution Approach 1:
The patent changes the fundamental operating parameter from voltage-controlled analog mixing to current-controlled digital switching. By using current mirrors with digitally controlled switching, the system achieves better PVT stability because current mirrors inherently compensate for process and temperature variations, and digital control codes remain stable across voltage and temperature changes.
Data Source
AI summary
A phase interpolator with a DAC outputting a first and second value responsive to a control code. A first current mirror generates a first current proportional to the first value. A second current mirror generates a second current proportional to the second value. A first FET pair comprising a first and second FET such that the source terminals of the first FET and the second FET are electrically connected and connect to the first current mirror. A second FET pair comprising a third and fourth FET such that the source terminals of the third FET and the fourth FET are electrically connected and connect to the second current mirror. A first terminal outputs a phase adjusted clock signal as compared to the clock signal, from the first FET and the third FET. A second terminal outputs an inverted phase adjusted clock signal, from the second FET and the fourth FET.