Hybrid Pipelined Packet Processing for Stateful Flow Scalability
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Solution Overview
Problem
Existing packet processing architectures are stateless, limiting their ability to manage high-speed, stateful network flows required by emerging applications like virtualization and AI, and they consume excessive power with increased network bandwidth.
Innovation Solution
A hybrid pipelined-data flow packet processing architecture that normalizes sequential and parallel data paths, using a dataflow controller to process packets based on dynamically updated states, policies, and scheduling data, with intelligent configuration of packet processing flows to support scalable and efficient stateful network flows.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional stateless packet processing architectures are used, then device complexity is reduced, but the ability to manage stateful network flows required by emerging applications is lost
Solution Approach 1:
The system segments packet processing into distinct functional stages including parsing, classification, state management, and action execution. Each stage is handled by specialized hardware components working in parallel, allowing stateful processing capabilities to be added without overwhelming the overall system complexity.
Solution Approach 2:
The architecture implements dynamic state management where connection states are maintained and updated in hardware buffers, allowing the system to adapt to emerging applications requiring stateful flows. The state management component dynamically allocates and manages buffer resources based on active connections.
2Productivity
If pipeline stages are increased to improve line rate, then processing speed improves, but power consumption increases
Solution Approach 1:
Multiple processing functions are merged into unified hardware components. For example, the parsing and classification stages are combined in a single pipeline, and state management is integrated with the forwarding decision logic, reducing the total number of separate pipeline stages while maintaining high line rates.
Solution Approach 2:
The system introduces intermediate buffering stages that allow data to be held and processed in parallel rather than requiring sequential pipeline stages. This mediator approach enables multiple packets to be processed simultaneously at different stages, improving throughput without proportionally increasing power consumption.
3Productivity
If RMT model is used for sequential data processing, then simplicity is maintained, but parallelism capability is limited
Solution Approach 1:
The system transitions from sequential single-dimension processing to multi-dimensional parallel processing by implementing multiple independent parsing pipelines that can simultaneously process different packet streams. Each pipeline operates independently, enabling true parallelism while maintaining the simplicity of the underlying RMT match-action model.
4Adaptability or versatility
If FPGA architectures are used for high parallelism, then processing speed improves, but support for stateful packet flows is lacking
Solution Approach 1:
The architecture creates a universal processing platform that combines the high-speed parallelism of FPGA-like structures with integrated state management capabilities. The system can handle both stateless high-throughput traffic and stateful application flows through a unified hardware architecture that dynamically adapts to different processing requirements.
Data Source
AI summary
Methods, devices, systems, and computer program products to provide a hybrid pipelined-data flow packet processing architecture by normalizing sequential and parallel data paths along with scaling in network compute and stateful network flows. The method includes receiving state data, policy data, scheduling data, and/or dataflow operation data. The method also includes processing data packets based on configured or dynamically updated states, policies, scheduling, and dataflow operations. The method includes performing arithmetic logic unit (ALU)/program execution operations on the data packets based on incoming and outgoing data and control planes. The method also includes intelligently configuring a packet processing flow based on at least one of the state data, the priority data, the scheduling data, and the dataflow operation data.