Hybrid Pitch-Split Lithography for IC Interconnects
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Solution Overview
Problem
Forming crossovers between adjacent parallel route tracks and separated lines in integrated circuits with desired lateral dimensions is problematic, especially at technology nodes beyond 28 nanometers using 193 nanometer illumination sources, which requires multiple pattern steps and complicates the tradeoff between fabrication costs and yield.
Innovation Solution
A process involving three interconnect patterns formed using photolithography with illumination sources capable of resolving features twice the pitch distance of the route tracks, allowing for the formation of metal interconnect lines with leads extending to specific points, enabling efficient metal interconnect formation and reducing space usage on the integrated circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple pattern steps are used to form metal interconnect layouts at 28 nanometer node and beyond using 193 nanometer illumination sources, then the desired pitch resolution is achieved, but the fabrication process complexity and cost increase
Solution Approach 1:
The patent applies segmentation by dividing the formation of metal interconnect layouts into multiple pattern steps (first interconnect pattern, second interconnect pattern, third interconnect pattern). Each pattern step forms a specific portion of the final interconnect structure, allowing the complex layout to be built incrementally using 193 nanometer illumination sources that can resolve features at twice the desired pitch distance.
Solution Approach 2:
The patent uses pitch-split decomposition to form interconnect patterns by utilizing multiple pitch dimensions. The first, second, and third interconnect patterns are formed with different pitch relationships, where each pattern contributes to the final structure in a different dimensional arrangement, enabling complex crossovers and adjacencies to be achieved within the resolution constraints of 193 nanometer illumination.
2Manufacturing precision
If multiple pattern steps are used to form metal interconnect layouts, then the desired pitch resolution is achieved, but the fabrication cost increases
Solution Approach 1:
The fabrication process is segmented into multiple pattern steps (first, second, and third interconnect patterns), each forming a specific portion of the final metal interconnect layout. This segmentation allows the use of existing 193 nanometer illumination sources rather than requiring more expensive alternative lithography tools, thereby managing fabrication costs while achieving the desired pitch resolution through systematic pattern decomposition.
3Reliability
If crossovers between adjacent parallel route tracks are formed with desired lateral dimensions, then the interconnect functionality is achieved, but the space requirements increase
Solution Approach 1:
The patent achieves crossovers between adjacent parallel route tracks by utilizing multiple pattern steps that operate in different dimensional arrangements. The first, second, and third interconnect patterns are formed with specific pitch relationships and lateral separations, allowing tracks to cross over each other in the vertical dimension (through layered patterning) rather than requiring excessive horizontal space, thus maintaining desired lateral dimensions while achieving the required interconnect functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the configuration of metal interconnect lines in less space, potentially lowering the cost of integrated circuit fabrication while maintaining desired dimensions and yield.
Implementation Method 1
forming a first interconnect pattern in a plurality of parallel route tracks, forming a second interconnect pattern in the plurality of parallel route tracks, and forming a third interconnect pattern in the plurality of parallel route tracks. The three interconnect patterns are formed using photolithography processes which have illumination sources capable of resolving features with a pitch distance in a direction perpendicular to the route tracks substantially equal to twice a pitch distance of the parallel route tracks
Data Source
AI summary
An integrated circuit may be formed by a process of forming a three interconnect patterns in a plurality of parallel route tracks, using photolithography processes which have illumination sources capable of a pitch distance twice the pitch distance of the parallel route tracks. The first interconnect pattern includes a first lead pattern which extends to a first point. The second interconnect pattern includes a second lead pattern which is parallel to and immediately adjacent to the first lead pattern. The third interconnect pattern includes a third lead pattern which is parallel to and immediately adjacent to the second pattern and which extends to a second point in the first instance of the parallel route tracks, laterally separated from the first point by a distance less than one and one-half times a space between adjacent patterns in the parallel route tracks.