Hybrid Microprocessor–PLD Architecture for Modular IPC Transfer
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Solution Overview
Problem
Existing programmable logic device (PLD) architectures face challenges in development and maintenance due to complex interconnections between functional blocks, limiting modularity, re-usability, and increasing costs and schedules, especially in aerospace applications.
Innovation Solution
A microprocessor-PLD hybrid architecture is introduced, incorporating a bus controller module that sequentially executes a set of bus controller instructions to facilitate high-data integrity and efficient command-data exchange between PLD modules, using a higher execution rate than the IPC interface, and employing error correcting encoding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a bus controller sequentially executes bus controller instructions to facilitate data exchange, then data transfer efficiency and payload are improved, but device complexity increases due to the need for instruction execution logic
Solution Approach 1:
The bus controller acts as an intermediary component between the microprocessor and PLD modules, managing data exchange through sequential instruction execution. This mediator approach allows complex data transfer operations to be coordinated without requiring direct complex interconnections between all components, thus improving data transfer efficiency while containing complexity in a dedicated control unit.
Solution Approach 2:
The system is segmented into distinct functional components: a microprocessor, a bus controller with instruction execution capability, and multiple PLD modules. This segmentation allows the bus controller to handle data exchange operations independently, improving overall productivity while distributing complexity across modular components rather than concentrating it in the interconnection structure.
2Reliability
If error correcting encoding is employed to ensure high data integrity, then reliability is improved, but loss of information increases due to additional encoding overhead
Solution Approach 1:
Error correcting encoding is applied beforehand to data before transmission through the bus controller and between PLD modules. This prior cushioning approach protects data integrity by pre-processing data with error correction codes, ensuring reliable transmission without requiring retransmission, thus improving reliability while managing information overhead through efficient encoding schemes.
3Productivity
If the command execution rate is greater than the IPC interface rate, then productivity is improved, but device complexity increases due to rate matching requirements
Solution Approach 1:
The bus controller serves as an intermediary that bridges the speed mismatch between the high-rate command execution logic and the lower-rate IPC interface. It buffers and manages the flow of commands and data, allowing the internal command execution rate to exceed the external interface rate without requiring complex synchronous coordination, thus improving productivity while containing complexity in the buffer management logic.
Solution Approach 2:
Commands are buffered and prepared in advance within the bus controller at the higher execution rate, before being transmitted through the slower IPC interface. This preliminary action allows the system to maintain high internal productivity while managing the slower external interface, separating the high-speed command processing from the lower-speed communication.
4Ease of manufacture
If a hybrid microprocessor-PLD architecture is implemented to improve modularity and re-usability, then ease of manufacture is improved, but device complexity increases due to integration requirements
Solution Approach 1:
The system is divided into separable modules: a microprocessor unit, a bus controller unit, and multiple PLD modules that can be independently designed, tested, and manufactured. This segmentation improves modularity and re-usability, allowing these components to be manufactured separately and then integrated through standardized interfaces, thus improving ease of manufacture while managing integration complexity through interface standardization.
Solution Approach 2:
The bus controller is designed as a universal interface that can work with multiple different PLD modules and microprocessor types through standardized communication protocols. This multi-functionality allows the same bus controller design to be reused across different configurations, improving ease of manufacture and re-usability while reducing integration complexity through standardized interfaces.
Data Source
AI summary
A microprocessor-PLD hybrid architecture includes an IPC microprocessor and a PLD in signal communication with the IPC microprocessor via an IPC interface. The IPC microprocessor outputs a data read command to initiate a data read operation or a data write command. The PLD includes a plurality of PLD modules that store data and a bus controller. The bus controller communicates with the plurality of PLD modules via a plurality of PLD interfaces and is configured to sequentially execute a set of bus controller instructions. The bus controller reads data from a target PLD module from among the plurality of PLD modules in response to receiving the data read command, and transfers the data to the IPC microprocessor. The bus controller receives data from the IPC microprocessor and stores the data in a target PLD module from among the plurality of PLD modules in response to receiving the data write command.