Hybrid Analog-Digital PLL for Low-Jitter Event Synchronization
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Solution Overview
Problem
Digital audio systems face challenges in generating a stable low-jitter clock signal from timing references with high jitter, and existing synchronization circuits are limited in their ability to synchronize audio streams with video lines or frames due to constraints on loop bandwidth and intermediate clock signal frequency.
Innovation Solution
A hybrid analog/digital PLL circuit that uses a numerically-controlled analog oscillator and a digital phase-frequency detector to generate a low-jitter clock signal, with a high-level synchronization event mechanism to reset phase errors and synchronize with video or frame events, incorporating a digital loop filter and event/frame detector for improved synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a traditional analog phase-lock loop is used to generate a stable clock signal from a jittery timing reference, then the clock signal stability is improved, but the loop bandwidth must be kept low which limits the jitter reduction performance
Solution Approach 1:
The invention divides the phase-lock loop into two separate loops: a digital phase-lock loop that operates at high frequency to remove jitter, and an analog phase-lock loop that operates at lower frequency to remove oscillator noise. This segmentation allows each loop to be optimized for its specific function without the conflicting bandwidth requirements of a single loop.
Solution Approach 2:
The invention introduces an intermediate clock signal as a mediator between the jittery timing reference and the final stable clock output. The digital phase-lock loop first generates an intermediate clock with reduced jitter, which then serves as the reference for the analog phase-lock loop to generate the final low-noise clock signal.
2Measurement precision
If the loop bandwidth is increased to improve jitter reduction, then the jitter removal capability is improved, but the analog oscillator noise is also amplified
Solution Approach 1:
The invention segments the frequency domain into two regions: high-frequency jitter components are removed by the digital phase-lock loop with high loop bandwidth, while low-frequency oscillator noise is removed by the analog phase-lock loop with low loop bandwidth. This segmentation resolves the contradiction by assigning different bandwidth optimization goals to different loops.
Solution Approach 2:
The digital phase-lock loop uses excessive action by operating at a much higher frequency than the final clock rate, allowing it to aggressively remove jitter components without being constrained by the bandwidth limitations that would affect the analog oscillator noise performance.
3Adaptability or versatility
If a numerically-controlled oscillator is used to provide frequency control, then the frequency flexibility is improved, but the intermediate clock signal frequency limits the synchronizing circuit performance
Solution Approach 1:
The invention resolves the frequency limitation by transitioning to a time-domain approach where the numerically-controlled oscillator generates a high-frequency intermediate clock that is then divided down. This dimensional change from direct frequency synthesis to time-domain sampling and division allows the system to achieve both frequency flexibility and high performance.
Solution Approach 2:
The numerically-controlled oscillator performs preliminary action by generating an intermediate clock signal at a high frequency that exceeds the final clock rate. This preliminary high-frequency signal is then divided down to the desired frequency, allowing the synchronizing circuit to operate at optimal performance levels before the final frequency conversion.
4Device complexity
If the phase comparator is limited to single-bit information at intermediate clock frequency, then the circuit complexity is reduced, but the effective information update rate is limited
Solution Approach 1:
The invention uses periodic action by operating the simple single-bit phase comparator at a high intermediate clock frequency. The periodic sampling at this high rate effectively increases the information update rate despite the simplicity of the comparator, because more samples are taken per unit time.
Solution Approach 2:
The high-frequency intermediate clock signal performs preliminary action by providing multiple phase comparison opportunities before the final clock signal is generated. This preliminary high-rate sampling increases the effective information update rate without requiring a complex phase comparator.
Data Source
AI summary
A hybrid analog/digital phase-lock loop with high-level event synchronization provides a mechanism for generating a low-jitter clock from a timing reference that has a high jitter level and synchronizing the output clock to high-level events. A numerically-controlled analog oscillator provides a clock output and a counter divides the frequency of the clock output to provide input to a digital phase-frequency detector for detecting an on-going phase-frequency difference between the timing reference and the output of the counter. A synchronization circuit detects or receives a high-level event signal, and resets the on-going phase-frequency difference and optionally the counter to synchronize the clock output with the events. The synchronization circuit may have an arming input to enable the synchronization circuit to signal a next event. Another clock output divider may be included to generate a timing reference output, and the other clock divider also reset in response to a detected event.