Hybrid PLL Loop Filter With Sample-and-Hold Jitter Reduction
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Solution Overview
Problem
Phase-locked-loop (PLL) circuits in wireless communication devices experience signal jitter due to unwanted variations in control voltage, leading to noise and degradation in signal-to-noise ratio (SNR), as minor voltage ripples cause frequency and phase variations in the generated signals.
Innovation Solution
A PLL circuit employing a hybrid loop filter with sample and hold capacitors to reduce ripple in the control voltage, using a charge pump circuit to charge/discharge a sample capacitor based on phase differences and a loop filter circuit to store the sample voltage in a hold capacitor, generating a proportional control voltage that minimizes frequency variations and noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional loop filter circuit is used in the PLL circuit, then the circuit structure is simple, but the control voltage contains ripple which causes frequency and phase variations (jitter) in the generated signal
Solution Approach 1:
The loop filter circuit is segmented into multiple functional blocks: a proportional control path with sample capacitor and hold capacitor, and an integral control path with separate capacitor. This segmentation allows each component to perform its specific function optimally while reducing overall signal jitter in the control voltage provided to the VCO.
2Reliability
If the control voltage is stabilized to reduce jitter, then signal quality improves, but the loop filter circuit requires additional capacitors and switches increasing circuit complexity
Solution Approach 1:
The hold capacitor is merged into the proportional control path and directly coupled to the VCO, combining the functions of voltage stabilization and direct VCO control. This integration reduces the number of separate components needed while achieving effective jitter reduction in the control voltage.
Solution Approach 2:
The hold capacitor acts as an intermediary element between the charge pump circuit and the VCO, smoothing out voltage ripples before they reach the VCO. This mediator component effectively reduces jitter without requiring complex filtering circuits.
3Reliability
If a hold capacitor is added to store sample voltage and reduce ripple, then frequency variations are minimized, but the loop filter circuit area increases
Solution Approach 1:
The hold capacitor stores the sample voltage in advance before it is provided to the VCO, preparing a stable voltage level that minimizes subsequent frequency variations. This preliminary voltage storage action prevents jitter rather than correcting it, achieving frequency stability without requiring oversized filtering components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces signal jitter and noise in transmitted signals by stabilizing the control voltage, improving the signal-to-noise ratio and maintaining phase lock with the reference signal.
Implementation Method 1
The charge pump circuit charges/discharges a sample capacitor of the loop filter circuit to a sample voltage based on a phase difference (timing difference) between the generated analog signal and the reference signal
Implementation Method 2
The loop filter circuit stores the sample voltage as a proportional control voltage in a hold capacitor to reduce or avoid ripple in the control voltage
Data Source
AI summary
A phase-locked loop (PLL) circuit generates an analog signal in phase-lock with a reference signal at a reference frequency. The PLL circuit includes a charge pump circuit, a loop filter circuit, a feedback divider, and a voltage controlled oscillator (VCO). The charge pump circuit charges a sample capacitor of the loop filter circuit to a sample voltage based on a phase difference between the generated analog signal and the reference signal. The loop filter circuit stores the sample voltage as a proportional control voltage in a hold capacitor to reduce or avoid ripple in the control voltage that causes jitter in the analog signal. The loop filter circuit also provides the sample voltage to an integral component circuit comprising a comparator and digital accumulator producing an integral control. The VCO generates the analog signal at a frequency based on the proportional control voltage and the integral control voltage.