Hybrid PLL Jitter Suppression Using Digital Delay Filtering
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Phase locked loops (PLLs) produce output signals with residual jitter and PLL errors that affect synchronization with reference signals, which existing technologies fail to effectively filter and manage.
Innovation Solution
A system comprising a phase locked loop (PLL) device with a delay element and digital phase detector that filters PLL errors from the output signal in steady-state mode, and operates in transparent mode when not locked, using a digital accumulator to generate control signals for the delay element to adjust the output signal's rising edge and filter PLL errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a phase locked loop is used to produce synchronized clock signals, then frequency and phase matching with reference signals is achieved, but residual jitter and PLL errors remain in the output signal
Solution Approach 1:
The patent segments the PLL error filtering function into a separate delay element that operates independently from the main PLL loop. This delay element specifically targets and filters residual jitter without affecting the overall synchronization function, allowing the system to maintain frequency/phase matching while removing harmful jitter components.
Solution Approach 2:
The delay element acts as an intermediary component between the PLL output and the final synchronized signal. It mediates the conflict between maintaining PLL lock (which produces jitter) and achieving clean output signals, by selectively filtering jitter while preserving the synchronized timing information.
2Measurement precision
If filtering is applied to reduce jitter in the output signal, then synchronization accuracy improves, but the system complexity increases
Solution Approach 1:
The patent extracts the jitter filtering function from the complex analog PLL filtering mechanisms and implements it as a separate, simpler delay element. This extracted component performs jitter reduction through digital delay techniques rather than complex analog filtering, reducing overall system complexity while maintaining effectiveness.
Solution Approach 2:
The patent replaces traditional analog filtering mechanisms (mechanical/electrical RC circuits, active filters) with a digital delay-based filtering approach. This substitution simplifies the filtering mechanism by using digital signal processing techniques instead of complex analog components, reducing device complexity while achieving the same jitter reduction goal.
3Reliability
If the delay element operates in transparent mode during acquisition, then the PLL can lock to the reference signal, but jitter filtering is not applied
Solution Approach 1:
The delay element dynamically switches between two operational modes: transparent mode during acquisition/lock and filtering mode during steady-state operation. This dynamic behavior allows the system to prioritize acquisition reliability first, then transition to jitter filtering once locked, optimizing both reliability and signal quality at different operational stages.
Solution Approach 2:
The system periodically transitions between transparent and filtering modes based on the PLL lock status. During acquisition, the transparent mode allows rapid locking; once locked, the system periodically maintains filtering mode to continuously reduce jitter, creating a rhythmic operational pattern that balances acquisition speed with ongoing signal quality.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A method for filtering noise. The method may include obtaining an output signal from a phase locked loop (PLL) device. The method may include determining, using a digital phase detector and the output signal, an amount of PLL error produced by the PLL device. The method may include filtering, using a delay element and a digital filter, a portion of the amount of PLL error from the output signal to produce a filtered signal in response to determining the amount of PLL error produced by the PLL device.