Hybrid PLL Control Paths for Low-Spur Phase Locking
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Solution Overview
Problem
Hybrid PLL architectures face challenges in achieving accurate phase and frequency locking due to sensitivity to noise and the need for complex analog circuitry, particularly in all-digital implementations which can result in spurs in the output spectrum and deterministic jitter.
Innovation Solution
A hybrid PLL architecture incorporating a digital integrating control path and an analog proportional control path, utilizing a phase and frequency detector, digitally controlled oscillator, charge pump circuit, and sigma-delta modulators, which reduces the complexity of analog circuitry and noise sensitivity by employing a simplified charge pump architecture and RC filters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If an all-digital PLL architecture is used, then portability and scalability are improved, but spurs appear in the output spectrum and deterministic jitter increases
Solution Approach 1:
The patent combines digital and analog components in a hybrid architecture. The phase-frequency detector and digital integrator are implemented digitally for scalability, while the proportional control path uses analog circuitry (charge pump with current sources and switches) to reduce spurs and jitter in the output spectrum by providing continuous analog control signals to the DCO.
2Measurement precision
If complex analog circuitry is used in hybrid PLL architecture, then phase locking accuracy is improved, but device complexity increases
Solution Approach 1:
The control path is segmented into two independent paths: a digital integrating path for long-term frequency accuracy and an analog proportional path for short-term phase correction. This segmentation allows each path to be optimized independently, reducing overall complexity while maintaining high phase locking accuracy through the coordinated operation of both paths.
3Ease of manufacture
If all-digital control paths are used, then manufacturing simplicity is improved, but noise sensitivity increases
Solution Approach 1:
The analog proportional control path acts as an intermediary between the digital phase-frequency detector and the digital controlled oscillator. It converts digital control signals into analog control voltages that can more effectively suppress noise and jitter, providing a buffering layer that reduces noise sensitivity while maintaining manufacturing simplicity through the use of standard analog building blocks.
Data Source
AI summary
Phase locked loop (PLL) architectures are provided such as hybrid PLL architectures having separate digital integrating control paths and analog proportional control paths. An analog proportional control path can be implemented with a charge pump circuit that includes resistors in series with CMOS switches to generate control currents (e.g., Up/Down control currents) which are used to adjust a control voltage applied to a digitally controlled oscillator. A digital integrating control path can be implemented with a series of sigma-delta modulators that operate at different frequencies to convert higher bit data signals to lower bit data signals along the digital integrating control path. A single phase frequency detector may be implemented to generate control signals that separately control the analog proportional and digital integrating control paths.