Hybrid PLL Circuit PSRR Improvement via Segmented Power Supplies
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Solution Overview
Problem
Existing Phase Locked Loop (PLL) circuits face challenges in improving Power Supply Rejection Ratio (PSRR) while minimizing the area and power consumption of the regulator, which can be influenced by noise and require larger circuit sizes.
Innovation Solution
A hybrid PLL circuit design incorporating a proportional path and an integral path with distinct power supply systems, utilizing a current-controlled oscillator driver and a current-controlled oscillator, along with a phase frequency detector, to manage phase differences and oscillation operations, thereby enhancing PSRR without increasing circuit size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a regulator is used to drive the VCO in the integral path, then Power Supply Rejection Ratio (PSRR) is improved, but the area and power consumption of the regulator increase
Solution Approach 1:
The patent divides the PLL circuit into two separate power supply systems: a first power supply system (higher voltage) for the proportional path and regulator, and a second power supply system (lower voltage) for the integral path and VCO. This segmentation allows the regulator to operate at higher voltage for better PSRR while the VCO operates at lower voltage to reduce noise susceptibility and overall power consumption.
Solution Approach 2:
Different parts of the circuit are assigned different power supply characteristics: the proportional path receives higher voltage for strong drive capability and PSRR, while the integral path and VCO receive lower voltage for noise reduction. This local quality differentiation optimizes each subsystem's performance for its specific function.
2Reliability
If a regulator is used to drive the VCO in the integral path, then Power Supply Rejection Ratio (PSRR) is improved, but power consumption of the regulator increases
Solution Approach 1:
The patent divides the PLL circuit into two separate power supply systems: a first power supply system (higher voltage) for the proportional path and regulator, and a second power supply system (lower voltage) for the integral path and VCO. This segmentation allows the regulator to operate at higher voltage for better PSRR while the VCO operates at lower voltage to reduce noise susceptibility and overall power consumption.
Solution Approach 2:
Different parts of the circuit are assigned different power supply characteristics: the proportional path receives higher voltage for strong drive capability and PSRR, while the integral path and VCO receive lower voltage for noise reduction. This local quality differentiation optimizes each subsystem's performance for its specific function.
3Object-affected harmful factors
If the regulator size is increased to reduce noise, then noise of the regulator is reduced, but the circuit size becomes large
Solution Approach 1:
The patent divides the PLL circuit into two separate power supply systems: a first power supply system (higher voltage) for the proportional path and regulator, and a second power supply system (lower voltage) for the integral path and VCO. This segmentation allows the regulator to operate at higher voltage for better PSRR while the VCO operates at lower voltage to reduce noise susceptibility and overall power consumption.
Solution Approach 2:
The patent changes the voltage parameter differently for different parts of the circuit: higher voltage for the regulator to improve PSRR without increasing size, and lower voltage for the VCO to reduce noise susceptibility. This parameter differentiation resolves the contradiction between noise reduction and circuit size.
Data Source
AI summary
An object is to improve Power Supply Rejection Ratio in a PLL circuit. A proportional path 103 is provided in a first power supply system 101 and outputs analog proportional signal AP according to a detection signal DET. An integral path 104 is provided in a second power supply system and outputs an analog integral signal AI according to the DET. A CCO driver 16 is provided in the first power supply system 101 and outputs control current ICCO according to the AP and the AI. A CCO 17 is provided in the second power supply system 102 and outputs an output signal Fout according to the ICCO. A phase frequency detector 11 is provided in the second power supply system 102 and configured to detect a phase difference between a reference signal Fref and a signal FM obtained by feeding back the Fout and then outputs the DET.


