Hybrid Digital PLL with Dual-Loop Wide Locking Range

Solution Overview

Problem

Existing digital phase locked loops (DPLLs) face limitations in locking range due to reliance on phase error measurement, which restricts frequency correction and increases noise when attempting to expand the locking range.

Innovation Solution

Incorporating a second control loop that measures and corrects frequency differences between the reference and feedback signals, using a PI controller or complex algorithm to force frequency errors to zero, thereby increasing the locking range without increasing phase error-based loop gain.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If the loop bandwidth is reduced to reduce jitter, then the noise is reduced, but the convergence time increases significantly

Engineering Contradiction:

ImprovejitterVSAvoidconvergence time

Core Design Contradiction:

Object-affected harmful factorsVSLoss of time

Solution Approach 1:

The control loop is segmented into two independent paths: a phase error measurement path with narrow bandwidth for low jitter, and a frequency error measurement path with wide bandwidth for fast convergence. Each path processes different error components and feeds control signals to the DCO, allowing simultaneous optimization of both jitter and convergence time.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The invention adds a new dimension to the control system by introducing frequency error measurement as a separate control variable alongside phase error measurement. This transforms the single-loop phase-controlled system into a two-dimensional control space with both phase and frequency error corrections, enabling independent optimization of bandwidth for each control objective.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Loss of time

If the loop bandwidth is increased to reduce convergence time, then the convergence time is reduced, but the jitter increases

Engineering Contradiction:

Improveconvergence timeVSAvoidjitter

Core Design Contradiction:

Loss of timeVSObject-affected harmful factors

Solution Approach 1:

The control loop is segmented into two independent paths: a phase error measurement path with narrow bandwidth for low jitter, and a frequency error measurement path with wide bandwidth for fast convergence. Each path processes different error components and feeds control signals to the DCO, allowing simultaneous optimization of both jitter and convergence time.

Inventive Principle:

Principle #1Segmentation

3Adaptability or versatility

If the locking range is expanded by increasing loop gain, then the locking range increases, but the noise increases

Engineering Contradiction:

Improvelocking rangeVSAvoidnoise

Core Design Contradiction:

Adaptability or versatilityVSObject-affected harmful factors

Solution Approach 1:

The invention adds a new dimension to the control system by introducing frequency error measurement as a separate control variable alongside phase error measurement. This transforms the single-loop phase-controlled system into a two-dimensional control space with both phase and frequency error corrections, enabling independent optimization of bandwidth for each control objective.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The system changes the control parameters by switching from purely phase-error-based control to dual parameter control using both phase error and frequency error measurements. This allows the locking range to be expanded through frequency error correction without requiring increased loop gain in the phase path, thereby avoiding noise amplification.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS10243572B2Hybrid phase locked loop having wide locking range

Publication Date: 2019.03.26 MICROSEMI SOC CORP

AI summary

A digital phased lock loop includes a digital controlled oscillator configured to produce an output signal at an output signal frequency, and a phase comparator configured to compare the output signal or a signal derived from the output signal, with a reference signal at a reference signal frequency or a signal derived from the reference signal to produce a phase error signal. A first loop filter produces a first control signal for the digital controlled oscillator. A frequency error measuring circuit produces a frequency error signal that directly represents a frequency difference between the output signal frequency and the reference signal frequency. A second loop filter produces a second control signal for the digital controlled oscillator from an output of the frequency error measuring circuit. A circuit combines the first and second control signals and providing the combined control signals to the digital controlled oscillator.