Hybrid PoE PSE Architecture with Parallel FETs
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Solution Overview
Problem
Existing power over Ethernet (PoE) power sourcing equipment architectures face limitations in flexibility for variable maximum power delivery, with integrated FET designs optimized for specific power levels restricting further power applications and external FET designs being costly and space-prohibitive.
Innovation Solution
A hybrid power FET approach combining internal and external FETs, where the internal FET is optimized for a target application and the external FET is added in parallel to boost power, reducing overall resistance and enabling higher power delivery with smaller external FETs, thus offering design flexibility and cost-effectiveness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If an integrated FET design is used, then the PSE achieves cost-effectiveness and integration benefits, but the maximum power delivery is restricted to a specific level
Solution Approach 1:
The FET system is segmented into two independent components: an integrated FET and an external FET. The integrated FET handles baseline power delivery with full integration benefits, while the external FET provides additional power capacity when needed. This segmentation allows the system to achieve both cost-effectiveness (through the integrated portion) and adaptability (through the optional external addition).
Solution Approach 2:
The PSE architecture is designed to support multiple power delivery levels by universally accommodating both integrated-only configurations and hybrid configurations. The system can adapt its power delivery capability based on whether an external FET is present, making the architecture universally applicable to different power requirements without sacrificing integration benefits in any configuration.
2Power
If an external FET is added in parallel to the integrated FET, then the maximum power delivery is increased, but the device complexity and space requirements increase
Solution Approach 1:
The external FET is merged with the integrated FET in a parallel configuration, combining their power delivery capabilities. This merging approach allows the system to achieve higher maximum power delivery while maintaining a relatively simple architecture, as the two FETs work together as a unified power delivery system rather than requiring complex power management circuitry.
3Power
If an external FET is added in parallel to the integrated FET, then the maximum power delivery is increased, but the space and cooling requirements increase
Solution Approach 1:
The external FET is positioned to utilize available space in the PSE device, with its placement optimized to minimize impact on overall device footprint. The thermal management approach applies local quality by directing cooling resources to the external FET based on its specific thermal characteristics and location, rather than requiring uniform cooling across the entire device, thus reducing overall space requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The hybrid FET design allows for flexible and efficient power delivery across a range of applications, reducing costs and enabling higher port densities while accommodating space and cooling constraints, without sacrificing the integration benefits of internal FET architectures.
Implementation Method 1
the external FET is connected in parallel to an internal FET in a PSE chip
Data Source
AI summary
A power over Ethernet (PoE) power sourcing equipment (PSE) architecture for variable maximum power delivery. PoE PSE subsystems rely on some control to “turn on” a power field effect transistor (FET), which allows current to be transmitted to a powered device (PD). A hybrid approach is provided where an internal FET can be augmented with an external FET to provide an architecture that can be flexibly applied to applications with various space, cost and cooling limitations. The maximum delivered power can also be boosted with the addition of an external FET to the internal FET.