Hybrid Poly Gate Structure for Multi-Gate Transistor Density
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Solution Overview
Problem
Existing techniques for scaling down semiconductor integrated circuits, such as poly on diffusion edge (PODE) and continuous poly on diffusion edge (CPODE) schemes, fail to achieve sufficient device density, cell isolation, and performance required for aggressively scaled circuits and devices.
Innovation Solution
A hybrid poly (hybrid PO) scheme is introduced, which involves a cut fin process and filling the cut fin region partially with a high-K dielectric, providing aggressive cell abutment and reducing the contacted poly pitch (CPP) by 50% compared to PODE and 25% compared to CPODE, suitable for multi-gate devices like FinFETs and GAA transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If poly on diffusion edge (PODE) or continuous poly on diffusion edge (CPODE) schemes are used to scale contacted poly pitch, then gate pitch reduction is achieved, but device density and cell isolation are insufficient
Solution Approach 1:
The patent segments the gate pitch into multiple components by introducing separate contact regions and isolation structures. The gate electrode is divided into multiple segments with individual contacts, allowing independent optimization of each segment's pitch and isolation, thereby achieving both reduced overall pitch and improved device density
Solution Approach 2:
The patent transitions from two-dimensional planar scaling to three-dimensional vertical structures by forming fins or nanosheets that extend vertically from the substrate. This vertical dimension allows gate electrodes to wrap around channels in multiple directions (FinFET, GAA structures), achieving superior gate control and reduced pitch without compromising device isolation
2Productivity
If conventional scaling approaches are used, then production efficiency is improved, but the level of device density and cell isolation required for aggressively scaled circuits is not achieved
Solution Approach 1:
The patent performs preliminary patterning and isolation structure formation before final gate electrode deposition. By pre-defining contact regions and isolation trenches, the subsequent gate fabrication proceeds more efficiently with better precision, achieving high device density without sacrificing production throughput
Solution Approach 2:
The patent changes critical geometric parameters including fin height, nanosheet thickness, and gate wrap-around angles to optimize the balance between device density and isolation. These parameter adjustments enable aggressive scaling while maintaining manufacturing feasibility and device performance
Data Source
AI summary
A semiconductor device includes a first transistor having a first gate structure and a first source/drain feature adjacent to the first gate structure. The semiconductor device further includes a second transistor having a second gate structure and a second source/drain feature adjacent to the second gate structure. In some examples, the semiconductor device further includes a hybrid poly layer disposed between the first transistor and the second transistor. The hybrid poly layer is adjacent to and in contact with each of the first source/drain feature and the second source/drain feature, and the hybrid poly layer provides isolation between the first transistor and the second transistor.