Hybrid Power Converter Packaging for Mixed-Voltage FET Integration
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Solution Overview
Problem
Existing power converter technologies face challenges in achieving efficient and cost-effective integration of field effect transistors (FETs) with different voltage ratings on a single substrate, while also requiring isolated devices and low packaging costs.
Innovation Solution
The hybrid (co-packaged) approach, which involves packaging lateral double-diffused metal-oxide-semiconductor (LDMOS) FET devices with a power converter controller, allowing for the integration of FETs with different voltage ratings on a single wafer without increasing the mask count, and reducing packaging costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If FETs with different voltage ratings are integrated on a single substrate, then device functionality and power conversion capability are improved, but device isolation and manufacturing complexity worsen
Solution Approach 1:
The substrate is divided into multiple isolated regions or islands, each designed to accommodate FETs with specific voltage ratings. Physical separation through trenches or dielectric layers ensures electrical isolation between different voltage domains, allowing simultaneous integration of FETs with different voltage ratings while maintaining proper isolation.
Solution Approach 2:
Different regions of the substrate are assigned different electrical characteristics and isolation levels according to the specific voltage rating requirements of FETs in those regions. High-voltage FETs are placed in regions with enhanced isolation structures, while low-voltage FETs use standard isolation, optimizing both functionality and manufacturing.
2Area of stationary object
If hybrid co-packaging approach is used, then packaging cost and area footprint are reduced, but manufacturing precision requirements increase
Solution Approach 1:
Multiple separate packages (power FETs and controller) are merged into a single hybrid package. The controller die and power FET dies are co-packaged together with minimized inter-connect lengths, reducing overall package footprint while requiring precise alignment and attachment processes to ensure proper electrical connections.
Solution Approach 2:
Interconnection structures such as wire bonds, flip-chip bumps, or conductive paste are used as intermediaries to establish electrical connections between the controller die and power FET dies. These intermediary connection methods provide tolerance for alignment variations while maintaining low parasitic inductance and resistance.
3Reliability
If isolated FET devices are implemented, then voltage rating differentiation is achieved, but manufacturing process complexity increases
Solution Approach 1:
Isolation structures such as deep trenches, dielectric layers, or junction isolation are formed preliminarily during the fabrication process before FET fabrication. This preliminary isolation action simplifies subsequent processing steps and ensures proper voltage rating differentiation without requiring additional complex mask steps later in the process.
Solution Approach 2:
The isolation effectiveness is controlled by adjusting parameters such as trench depth, dielectric layer thickness, or doping concentrations in isolation regions. By changing these physical parameters rather than adding complex process steps, the manufacturing process remains relatively simple while achieving the required voltage rating differentiation.
Data Source
AI summary
Disclosed embodiments may include systems, devices, processes, and methods for fabricating and packaging power converters on an integrated circuit. In some embodiments, a power converter device may be processed and packaged using a hybrid (co-packaged) approach. The power converter includes a first integrated circuit die with a plurality of first switches and a plurality of second switches. The power converter further includes a second integrated circuit die including a controller circuit that is electrically coupled to control switching of the plurality of first switches and the plurality of second switches. The power converter may include additional integrated circuit dies coupled to the controller circuit. The plurality of first switches and the plurality of second switches may each include vertical double-diffused metal-oxide semiconductor field effect transistors. The plurality of first switches and the plurality of second switches may each include lateral double-diffused metal-oxide semiconductor field effect transistors.