Hybrid Processing Units with Shared Circuitry for Power Domain Management
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Solution Overview
Problem
Current data processing systems face challenges in efficiently managing power consumption and processor performance scaling, particularly in portable devices, due to complex power supply and clocking systems, high static power consumption, and inefficient task migration between processors.
Innovation Solution
The system employs first and second processing circuitry operating in different power domains, with shared processing circuitry allowing for hybrid processing units to execute a single instruction stream, enabling direct state transfer and reducing power consumption by powering down higher efficiency circuitry, thus simplifying power management and improving task migration efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If dynamic voltage and frequency scaling (DVFS) is used to control power and performance, then power consumption is reduced, but the system requires relatively complex power supply and clocking systems
Solution Approach 1:
The system is divided into multiple power domains (first power domain, second power domain, shared power domain) that can be independently controlled. Each processing circuit operates in its own power domain, allowing selective power management without requiring complex voltage and frequency scaling across the entire system. This segmentation simplifies the power supply and clocking systems while maintaining power management capabilities.
2Use of energy by stationary object
If voltage scaling is used to reduce power consumption, then dynamic power is reduced, but transistors cannot operate below a certain characteristic minimum voltage and static power consumption is not eliminated
Solution Approach 1:
The invention extracts and removes entire processing circuits from the active power domain and places them in a powered-down state when not needed. This goes beyond voltage scaling by completely disconnecting power to unused processing circuits, thereby eliminating both dynamic and static power consumption for those circuits. The processing circuits can be selectively powered up or down based on workload requirements.
3Productivity
If heterogeneous multiprocessors are used to provide performance scaling, then different processing tasks can be executed concurrently, but task migration between processors requires saving and reloading processor state which takes considerable time
Solution Approach 1:
The system merges multiple processing circuits into a unified processing system that operates as a single processing entity. The shared processing circuitry and unified power domain allow for seamless task migration between processing circuits without requiring state saving and reloading. The processing circuits work together as an integrated unit, eliminating the time loss associated with traditional heterogeneous multiprocessor task migration.
4Productivity
If multiple processors are used to handle different processing tasks, then processing capability is increased, but any unused processors consume high power even temporarily
Solution Approach 1:
The system dynamically adjusts the power state of processing circuits based on real-time workload requirements. Processing circuits can be selectively activated or deactivated by switching power domains, allowing the system to maintain high processing capability when needed while minimizing power consumption when processing capacity is reduced. This dynamic power management ensures that unused processing circuits do not consume unnecessary power.
Data Source
AI summary
A data processing apparatus is provided comprising first processing circuitry, second processing circuitry and shared processing circuitry. The first processing circuitry and second processing circuitry are configured to operate in different first and second power domains respectively and the shared processing circuitry is configured to operate in a shared power domain. The data processing apparatus forms a uni-processing environment for executing a single instruction stream in which either the first processing circuitry and the shared processing circuitry operate together to execute the instruction stream or the second processing circuitry and the shared processing circuitry operate together to execute the single instruction stream. Execution flow transfer circuitry is provided for transferring at least one bit of processing-state restoration information between the two hybrid processing units.