Hybrid Processor Architecture for Post-Quantum Cryptography
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Solution Overview
Problem
The CRYSTALS-Dilithium cryptosystem, a lattice-based post-quantum digital signature scheme, faces performance and design flexibility issues due to complex and time-consuming computations, particularly in polynomial matrix-vector multiplication, which are not efficiently addressed by existing hardware accelerators.
Innovation Solution
A hybrid processor architecture is introduced, combining a hardware processor with software processor and an interconnection interface, featuring hardware accelerator modules for NTT, PWM, PWA, and SHAKE operations, utilizing AXI memory and peripheral interconnects for high-performance data exchange and configuration, to accelerate computationally intensive tasks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If pure software implementation is used for Dilithium computations, then device complexity is low, but computation time is excessive
Solution Approach 1:
The processor is segmented into distinct functional units: a software processor for control and coordination, hardware accelerator modules for computationally intensive tasks (NTT, PWM, PWA, SHAKE), and dedicated interconnection interfaces. This segmentation allows each component to be optimized independently, reducing overall computation time while managing complexity through modular design.
Solution Approach 2:
The AXI memory interconnect and AXI lite peripheral interconnect serve as intermediaries between the software processor and hardware accelerator modules. These interconnection interfaces enable efficient data exchange and coordination, reducing the complexity of direct integration while maintaining high performance.
2Productivity
If hardware accelerator modules are added to reduce computation time, then productivity increases, but device complexity increases
Solution Approach 1:
The hardware accelerator modules are designed with multi-functionality to handle various Dilithium operations (NTT, inverse NTT, point-wise multiplication, point-wise addition, SHAKE). This universal design allows a single hardware processor to support different security levels and computational requirements, increasing productivity while avoiding the need for multiple specialized hardware units.
Solution Approach 2:
The hardware processor includes configurable parameters and state machines that allow dynamic adaptation to different computational tasks and security levels. The system can switch between different operational modes (e.g., NTT mode, INTT mode) based on the specific cryptographic operation required, maintaining high productivity across varying workloads without requiring complex fixed architecture.
3Speed
If multiple interconnection interfaces are implemented for data exchange, then data transfer performance improves, but device complexity increases
Solution Approach 1:
Different interconnection interfaces are provided for different data transfer requirements: the AXI memory interconnect for high-speed computation data transfer between software processor and hardware accelerators, and the AXI lite peripheral interconnect for control signal and register access. This local quality approach optimizes data transfer performance for each specific communication path while managing overall system complexity through functional separation.
Data Source
AI summary
A processor for a cryptosystem. The processor comprises a hybrid processor architecture including a hardware processor, a software processor and an interconnection interface arranged to exchange data between the hardware processor and the software processor; wherein the hardware processor comprises a plurality of hardware accelerator modules arranged to perform computational tasks including at least one of number theoretic transforms (NTT) computation, arithmetic operations which are more time-consuming when being performed instead by the software-processor.