Hybrid Queue Structure for Unlimited Depth Data Transfer

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Solution Overview

Problem

Existing multi-tasking systems face challenges in managing bursts of messages from multiple processors, leading to processor stalls due to shallow hardware queues, and existing solutions that overflow into system memory occupy valuable space and do not fully eliminate stalling.

Innovation Solution

A hybrid queue structure that dynamically allocates memory for messages as nodes of a linked list, allowing the queue to overflow into system memory only when full, using a hardware queue with an auxiliary register to manage overflow and flags for synchronization, enabling efficient message processing without reserving unused memory space.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the hardware queue depth is increased to avoid processor stalls, then the stalling limit is pushed back, but the queue occupies an unreasonable surface area on the circuit

Engineering Contradiction:
Improveprocessor stalling avoidanceVSAvoidhardware queue surface area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The queue is segmented into a shallow hardware queue portion and a software-managed overflow portion in system memory. The hardware queue contains only enough slots to trigger overflow conditions, while the linked list structure in system memory provides the additional depth needed to avoid processor stalls without expanding hardware queue area.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The queue depth is extended from the hardware domain to the software/memory domain. By using a linked list structure in system memory that can be dynamically allocated, the queue effectively gains unlimited depth without requiring proportional hardware resources, transitioning the solution from spatial expansion to hierarchical organization.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If the hardware queue depth is increased to avoid processor stalls, then data production continuity is improved, but the hardware complexity and resource consumption increase

Engineering Contradiction:
Improvedata production continuityVSAvoidhardware queue complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

A hybrid queue management mechanism acts as an intermediary between the hardware queue and system memory. This mechanism includes overflow detection logic, linked list construction, and pointer management that coordinates between hardware and software components, enabling continuous data production without requiring the hardware queue to handle all overflow conditions alone.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If a reserved memory area is used for queue overflow, then the stalling limit is pushed back, but unused space is permanently removed from available system memory

Engineering Contradiction:
Improvestalling limitVSAvoidavailable system memory
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The queue overflow storage transitions from a static reserved memory area to a dynamic linked list structure. Memory pages are allocated on-demand as the queue fills and overflow occurs, and freed when queue slots become available. This dynamic allocation allows the same memory to serve both queue overflow and general system purposes at different times, maximizing memory utilization while maintaining reliability.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS10140020B2Data queue having an unlimited depth
Publication Date: 2018.11.27 STMICROELECTRONICS INT NV
  • US10140020B2 patent drawing
  • US10140020B2 patent drawing
  • US10140020B2 patent drawing

AI summary

A method for transferring messages from a producer element to a consumer element uses a memory shared between the producer element and the consumer element, and a hardware queue including several registers designed to contain addresses of the shared memory. The method includes the steps of storing each message for the consumer element in the shared memory in the form of a node of a linked list, including a pointer to a next node in the list, the pointer being initially void, writing successively the address of each node in a free slot of the queue, whereby the node identified by each slot of the queue is the first node of a linked list assigned to the slot, and when the queue is full, writing the address of the current node in memory, in the pointer of the last node of the linked list assigned to the last slot of the queue, whereby the current node is placed at the end of the linked list assigned to the last slot of the queue.