Hybrid IGZO-Silicon RAM Cell for Retention and MAC Linearity
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in achieving high integration density, fast operation speed, and long data retention time, particularly in SRAM and DRAM technologies, with SRAM requiring large areas and DRAM needing frequent refresh cycles.
Innovation Solution
A hybrid-structured random access memory combining a CMOS-based transistor with a silicon channel and an IGZO-based transistor, allowing for a smaller number of elements and improved threshold voltage distribution, enabling CIM operations like MAC operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If SRAM is used for high-speed operation, then operation speed is improved, but area increases and integration density decreases
Solution Approach 1:
The patent changes the material parameter of the channel from conventional silicon to IGZO (indium gallium zinc oxide), which fundamentally alters the transistor characteristics to achieve both high speed and small area. This material parameter change enables the transistor to operate at high speeds while occupying minimal space, resolving the contradiction between speed and area.
Solution Approach 2:
The patent employs a hybrid structure combining IGZO-based transistors with other materials in the memory cell architecture. This composite approach leverages the superior electron mobility and small size of IGZO transistors to achieve high-speed operation in a compact area, while maintaining compatibility with existing memory cell designs.
2Quantity of substance
If DRAM is used for high integration, then integration density is improved, but retention time decreases and refresh cycles are required
Solution Approach 1:
The patent changes the channel material parameter from silicon to IGZO, which provides superior off-state characteristics and reduced leakage current. This parameter change enables the memory cell to maintain data for longer periods without refresh, achieving both high integration density and long retention time simultaneously.
Solution Approach 2:
The patent segments the memory cell into distinct functional components with specialized transistors: IGZO-based transistors for data storage leveraging their low leakage properties, and silicon-based transistors for control functions. This segmentation allows each component to optimize its function, achieving high integration while maintaining long retention time.
3Quantity of substance
If memory cell elements are reduced for high integration, then integration density is improved, but variability of threshold voltage increases
Solution Approach 1:
The patent changes the material parameter to IGZO, which has superior uniformity and controllability in thin-film formation. This material parameter change reduces threshold voltage variability even in highly integrated designs with minimal elements, as IGZO allows for precise control of electrical characteristics through standardized fabrication processes.
Solution Approach 2:
The patent employs IGZO material which provides homogeneous electrical properties across the memory cell array. This homogeneity ensures consistent threshold voltage characteristics throughout the integrated structure, reducing variability even when using minimal number of elements per cell.
Data Source
AI summary
A random access memory according to one embodiment comprises: a first transistor having a channel formed of IGZO (Indium Gallium Zinc Oxide) material; second and third transistors having channels respectively formed of silicon material and connected in series; and a storage node, defined at a node where one terminal of the first transistor and a gate terminal of the second transistor are connected, in which data is stored.