Hybrid Read Clock Control for GDDR Memory Power and Signal Integrity
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Solution Overview
Problem
Existing DDR DRAM technologies, such as GDDR6, lack flexibility in managing the read clock signal (RCK) to optimize power consumption and signal integrity during varying workloads, particularly in high-performance graphics processing units (GPUs).
Innovation Solution
Implementing a hybrid read clock signal in GDDR memory that can be programmably controlled through mode registers to operate in 'always on', 'read-only', or 'disabled' modes, allowing dynamic adjustment of RCK behavior based on workload demands.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the read clock signal (RCK) is continuously generated in GDDR6 memory, then the memory can maintain synchronization readiness for high-speed data transmission, but power consumption increases due to unnecessary clock generation during infrequent read operations
Solution Approach 1:
The patent implements dynamic control of the read clock signal by introducing a mode register that allows the memory device to switch between different operational modes (always-on mode and read-request mode). In read-request mode, the RCK signal is generated only when a read command is received, rather than continuously. This dynamic adjustment enables the system to maintain high-speed data transmission capability when needed while reducing power consumption during periods of low read activity, directly resolving the contradiction between productivity and energy use.
2Speed
If the read clock signal (RCK) is generated at high frequency for fast read operations, then data transmission speed improves, but signal integrity deteriorates due to switching interference during write cycles
Solution Approach 1:
The patent employs periodic action by controlling the RCK signal to be generated only during specific periods when read operations are required, rather than continuously. The mode register enables the memory to enter a state where RCK is suppressed during write cycles and other non-read operations. This periodic generation of the clock signal eliminates switching interference during write cycles, maintaining signal integrity while still providing high-speed data transmission during read operations when the clock is active.
3Ease of operation
If the read clock signal (RCK) is always active to maintain synchronization, then the memory can respond immediately to read commands, but the memory controller design becomes complex due to interamble calculation requirements
Solution Approach 1:
The patent extracts the complexity of interamble calculation from the memory controller by implementing the RCK suppression functionality directly in the memory device through the mode register. When the mode register is set to read-request mode, the memory device itself manages the generation and suppression of the RCK signal based on command type, eliminating the need for the memory controller to perform complex interamble calculations. This transfers the control logic to the memory device, simplifying the overall system architecture while maintaining synchronization readiness.
Data Source
AI summary
A data processing system includes a memory responsive to receiving a read command to generate a hybrid read clock signal based on a setting of at least one mode register, and a data processor configured to program the at least one mode register including setting a read clock mode of the hybrid read clock signal to one of a plurality of settings. The plurality of settings includes an always on mode in which the hybrid read clock signal toggles continuously, and a read-only mode in which the hybrid read clock signal starts toggling in response to receiving the read command by the memory, and that continues to toggle at least to an end of a read postamble period following the read command. The data processor is also configured to receive data during a read cycle using the hybrid read clock signal.