Hybrid Read Scheme for Multi-Level Memory Cells
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Solution Overview
Problem
Conventional methods for reading data from multi-state memory cells are inefficient, requiring large amounts of hardware or suffering from slow read times, making them less than optimal for achieving good tradeoffs between cost, performance, and power consumption.
Innovation Solution
A hybrid read scheme that uses a sense amplifier and reference generators to apply different control voltages and reference signals in a two-step process, allowing for efficient differentiation between data states in multi-state memory cells, reducing hardware requirements and improving read speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional read methods are used for multi-state memory cells, then data can be read from the cells, but large amounts of hardware are required
Solution Approach 1:
The read operation is divided into multiple sequential steps, where each step reads one bit of the multi-bit data stored in the memory cell. This segmentation allows the use of simpler, single-bit read circuitry instead of complex multi-bit read hardware, resolving the contradiction between reliable data reading and hardware complexity
Solution Approach 2:
The patent employs periodic switching of wordline voltages to sequentially access different data states in the memory cell. By periodically changing the read voltage levels, the system can extract multiple bits of information using the same hardware infrastructure, reducing overall hardware requirements while maintaining reliable multi-state data reading
2Reliability
If traditional read methods are used for multi-state memory cells, then data can be read from the cells, but read times are slow
Solution Approach 1:
The patent performs preliminary sensing operations at multiple voltage thresholds before completing the full read operation. By pre-evaluating the memory cell state at different voltage levels, the system can quickly determine the stored data value and terminate the read operation early when possible, significantly reducing read time while maintaining accurate data reading
Solution Approach 2:
The read circuit incorporates feedback mechanisms that monitor the sensed current and adjust subsequent read operations based on previous measurements. This feedback allows the system to optimize read timing and voltage sequences, enabling faster extraction of multi-bit data while ensuring reading accuracy
3Reliability
If traditional read methods are used for multi-state memory cells, then data can be read from the cells, but power consumption is high
Solution Approach 1:
The patent dynamically changes read voltage parameters based on the memory cell state and required data precision. By adjusting voltage levels and read operation duration according to actual conditions, the system minimizes power consumption while ensuring reliable data reading from multi-state cells
Data Source
AI summary
Some aspects of the present disclosure relate to a read circuit that uses a hybrid read scheme as set forth herein. In this hybrid read scheme, a state machine, at a first time in the read operation, sets a reference signal SRef to a first reference value to induce determination of a first comparison result. At a second subsequent time in the read operation, the state machine sets the reference signal SRef to a second reference value, which is based on the first comparison result. Setting the reference signal to the second reference value induces determination of a second comparison result. The first and second comparison results are then used to determine the digital value read from the memory cell.