Hybrid Receiver Equalizer Reducing Multiplier Count

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Solution Overview

Problem

Existing receivers face a trade-off between the number of multipliers required and signal processing quality, as frequency-domain equalizers have fewer multipliers but slower tap coefficient updates, while time-domain equalizers have more multipliers but quicker updates.

Innovation Solution

A receiver that combines a discrete Fourier transform unit, a frequency-domain equalizer, an inverse discrete Fourier transform unit, and a time-domain equalizer to equalize signals, where only a portion of tap coefficients in both equalizers are updated, with faster-changing taps processed by the time-domain equalizer and slower-changing taps by the frequency-domain equalizer, reducing the overall number of multipliers needed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a frequency-domain equalizer is used, then the number of multipliers is reduced, but the tap coefficient update speed becomes slow

Engineering Contradiction:
Improvenumber of multipliersVSAvoidtap coefficient update speed
Core Design Contradiction:
Device complexityVSSpeed

Solution Approach 1:

The patent segments the equalizer functionality into two distinct components: a frequency-domain equalizer for reducing multiplier count and a time-domain equalizer for providing fast tap coefficient updates. This segmentation allows each component to specialize in its strength while compensating for the other's weakness, resolving the contradiction between device complexity and update speed.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent merges the frequency-domain equalizer and time-domain equalizer into a hybrid equalization system. The frequency-domain equalizer processes signals with fewer multipliers while the time-domain equalizer provides rapid adaptation, and their outputs are combined to achieve both low complexity and fast update capabilities simultaneously.

Inventive Principle:
Principle #5Merging (Combining)

2Speed

If a time-domain equalizer is used, then the tap coefficient update speed increases, but the chip area increases due to more multipliers

Engineering Contradiction:
Improvetap coefficient update speedVSAvoidchip area
Core Design Contradiction:
SpeedVSArea of stationary object

Solution Approach 1:

The patent segments the equalizer functionality into two distinct components: a frequency-domain equalizer for reducing multiplier count and a time-domain equalizer for providing fast tap coefficient updates. This segmentation allows each component to specialize in its strength while compensating for the other's weakness, resolving the contradiction between device complexity and update speed.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies local quality by having different equalizer components handle different aspects of signal processing: the frequency-domain equalizer handles the bulk of signal equalization with efficient FFT-based processing, while the time-domain equalizer provides localized fast adaptation for rapidly changing channel conditions, optimizing resource allocation across different functional regions.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS8472510B2Receiver and method for equalizing received signal
Publication Date: 2013.06.25 REALTEK SEMICON CORP
  • US8472510B2 patent drawing
  • US8472510B2 patent drawing
  • US8472510B2 patent drawing

AI summary

A receiver includes a discrete Fourier transform unit, a frequency-domain equalizer, an inverse discrete Fourier transform unit, a time-domain equalizer and an output circuit. The discrete Fourier transform unit is utilized for performing a discrete Fourier transform operation upon a received signal to generate a frequency-domain signal. The frequency-domain equalizer is utilized for equalizing the frequency-domain signal to generate an equalized frequency-domain signal. The inverse discrete Fourier transform unit is utilized for performing an inverse discrete Fourier transform operation upon the equalized frequency-domain signal to generate a first equalized time-domain signal. The time-domain equalizer is utilized for equalizing the received signal to generate a second equalized time-domain signal. The output circuit is utilized for generating a third equalized time-domain signal according to the first equalized time-domain signal and the second equalized time-domain signal.