Hybrid Register Server for Selective Emulated Register Mirroring
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Solution Overview
Problem
Conventional hybrid emulation systems are inefficient in managing hardware registers when using embedded software debuggers, as they require brute force methods to access emulation registers, leading to high computational resource usage and time consumption.
Innovation Solution
A hybrid register server is introduced to selectively mirror a subset of emulated registers, allowing embedded software debuggers to access them with configurable behaviors specified in a configuration file, and using a backdoor access mechanism to prevent side effects during debugging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If brute force approach is used to shadow all registers in emulation system on simulation system, then embedded software debugger can access emulation registers, but computational resource usage and time consumption increase significantly
Solution Approach 1:
The patent segments the register access problem by dividing registers into two categories: simulation registers accessible by the debugger, and emulation registers accessed through a hybrid register server. This segmentation allows the debugger to access only necessary registers through the simulation system while other registers are accessed through the emulation system, reducing the computational overhead of shadowing all registers.
Solution Approach 2:
The patent introduces a hybrid register server as an intermediary component that manages access to emulation registers. This server acts as a mediator between the debugger and the emulation system, allowing selective access to emulation registers without requiring the simulation system to shadow all registers, thus improving computational efficiency while maintaining debugger functionality.
2Adaptability or versatility
If all registers are shadowed on simulation system, then complete register access is achieved, but setup and management time increases
Solution Approach 1:
The patent applies partial action by implementing selective shadowing of registers. Instead of shadowing all emulation registers on the simulation system, only specific registers that require debugger access are shadowed. The hybrid register server manages access to the remaining emulation registers, reducing setup and management time while maintaining necessary access capabilities.
3Ease of operation
If simulation system manages all registers, then unified access mechanism is achieved, but computing resources on simulation system increase significantly
Solution Approach 1:
The hybrid register server serves as an intermediary that manages the division of register access responsibilities. It handles access to emulation registers while allowing the simulation system to manage simulation registers, creating a unified access mechanism that distributes computational load and reduces the energy consumption of the simulation system.
Solution Approach 2:
The hybrid register server provides multi-functionality by managing both simulation and emulation register access. This universal approach allows a single component to handle diverse register access requirements, simplifying the overall system architecture while reducing the computational burden on the simulation system.
Data Source
AI summary
One or more embodiments disclosed herein pertain to a hybrid emulation system for hybrid emulation of a design under test (DUT). The system comprises a hardware emulation system to emulate a first portion of the DUT during the hybrid emulation. The hardware emulation system includes emulated registers for the first portion of the DUT. The hybrid emulation system also comprises a simulation system to simulate a second portion of the DUT during the hybrid emulation. The hybrid emulation system additionally comprises a configuration file that identifies a subset of the emulated registers. The simulation system is configured with the configuration file to selectively mirror, during the hybrid emulation, the subset of the emulated registers identified by the configuration file.