Hybrid Voltage Regulator Switching for Wide Output Range and ESD Protection

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Solution Overview

Problem

Current voltage regulators, such as LDO regulators, have limited output signal level ranges, making them inadequate for supporting a wide range of distances and data rates in chip-to-chip communication, and lack electrostatic discharge (ESD) robustness.

Innovation Solution

A hybrid voltage regulator that combines n-type and p-type field effect transistors (NFET and PFET) with a switch control circuit to switch between different regulation modes, achieving a wide output signal level range and incorporating ESD protection by using pull-up PFETs to create a discharge path during ESD events.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a conventional LDO regulator with a single pass transistor is used, then the circuit structure is simple, but the output signal level range is limited

Engineering Contradiction:
Improveoutput signal level rangeVSAvoidcircuit structure
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The voltage regulator is segmented into two independent regulation paths: an n-type path (pass NFET1, amplifier AMP1) for low voltage regulation and a p-type path (pass PFET2, amplifier AMP2) for high voltage regulation. Each path operates independently and can be selected based on the required output voltage level, thereby expanding the overall output signal level range without requiring a completely complex redesign of the entire regulator.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The voltage regulator circuit is designed to perform multiple functions through the dual-path architecture. The same basic regulator structure (pass transistor + amplifier + feedback network) is replicated for both n-type and p-type operation, allowing the system to universally handle both low-voltage and high-voltage regulation requirements using a unified design paradigm that can adapt to different operating conditions.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If a conventional LDO regulator is used, then the circuit is simple, but ESD robustness is insufficient

Engineering Contradiction:
ImproveESD robustnessVSAvoidcircuit structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The circuit utilizes the inherent body diode of the pass PFET2 to create a beneficial ESD discharge path. During ESD events, the body diode naturally conducts, providing a low-impedance path for discharge current to flow safely. This converts what is typically considered a parasitic element (the body diode) into a useful protective feature that enhances ESD robustness without requiring additional external protection components.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Solution Approach 2:

The dual-path architecture with both n-type and p-type pass transistors provides pre-established protection pathways against ESD events. The presence of the pass PFET2 with its body diode creates a cushioning effect by providing a predetermined safe discharge route for ESD currents before they can damage sensitive circuit elements. This protective mechanism is built into the normal circuit operation rather than being an add-on feature.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS11378992B2Hybrid voltage regulator with a wide regulated voltage range
Publication Date: 2022.07.05 QUALCOMM INC
  • US11378992B2 patent drawing
  • US11378992B2 patent drawing
  • US11378992B2 patent drawing

AI summary

In certain aspects, a voltage regulator includes a pass n-type field effect transistor (NFET) coupled between a first voltage rail and a second voltage rail, and a pass p-type field effect transistor (PFET) coupled between the first voltage rail and the second voltage rail. The voltage regulator also includes a first amplifier having an output, a first switch coupled between the output of the first amplifier and a gate of the pass NFET, a second amplifier having an output, and a second switch coupled between the output of the second amplifier and a gate of the pass PFET, a third switch coupled between the gate of the pass NFET and a ground, and a fourth switch coupled between the gate of the pass PFET and the second voltage rail.