Hybrid RFFE Bus Addressing for One-Wire and Two-Wire Devices
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Solution Overview
Problem
Current serial communication systems face challenges in efficiently managing communication between devices using both one-wire and two-wire configurations over a shared Radio Frequency Front-End serial bus, particularly in mobile communication devices with increasing complexity and demand for simplified bus architectures.
Innovation Solution
The system configures subordinate devices with unique identifiers and uses sequence start conditions to determine whether clock pulses are needed in the clock signal, allowing for simultaneous communication with both one-wire and two-wire devices by transmitting datagrams accordingly, enabling flexible operation modes on a hybrid serial bus.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a shared serial bus is used to support both one-wire and two-wire devices, then the number of addressable devices increases and bus architecture is simplified, but the device complexity and protocol management complexity increase
Solution Approach 1:
The system dynamically switches between one-wire and two-wire communication modes based on the transaction type. The host device can select whether to provide clock pulses concurrently with data transmission (one-wire mode) or provide clock pulses separately (two-wire mode), allowing the same physical bus to adapt to different device types and communication requirements
Solution Approach 2:
The shared serial bus is designed to support multiple communication protocols and modes (one-wire, two-wire, RFFE, I2C, I3C) using the same physical infrastructure. By implementing a unified addressing scheme and mode selection mechanism, the bus can serve both one-wire and two-wire devices, as well as legacy protocols, without requiring separate dedicated buses for each protocol
2Reliability
If separate addressing schemes are used for one-wire and two-wire devices, then each device type can be uniquely identified, but the bus latency increases due to separate address translation tables
Solution Approach 1:
The patent merges the addressing schemes for one-wire and two-wire devices into a single unified address translation table. Instead of maintaining separate tables for different device types, the system uses a single table that can map addresses for both one-wire devices (when clock pulses are provided concurrently) and two-wire devices (when clock pulses are provided separately), eliminating the need for separate address lookups and reducing bus latency
Data Source
AI summary
A data communication apparatus coupled to a serial bus has a protocol controller that configures a first plurality of subordinate devices with device identifiers unique within the first plurality of subordinate devices and configures a second plurality of subordinate devices with device identifiers unique within the second plurality of subordinate devices. A sequence start condition transmitted over the serial bus indicates either a first communication mode in which a clock signal is provided to the serial bus or a second communication mode in which no clock signal is provided. A device identifier associated with the first plurality of subordinate devices is used to transmit a first datagram over the serial bus in the first communication mode, and a device identifier associated with the second plurality of subordinate devices is used to transmit a second datagram over the serial bus in the second communication mode.