Hybrid Ring Bus Interconnect Dynamic Router Power Latency

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Solution Overview

Problem

Current bus interconnects in processor-based systems face challenges in balancing performance and power consumption, as lowering bus clock frequency to reduce power consumption increases latency and degrades performance, while higher frequencies consume more power, and existing architectures like ring buses and crossbar interconnects have limitations in scalability and bandwidth.

Innovation Solution

A processor-based system hybrid ring bus interconnect that incorporates multiple ring buses with inter-ring routers dynamically directing bus transaction messages based on bandwidth requirements, allowing for shorter routes and reduced power consumption by activating or deactivating ring buses as needed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by stationary object

If bus clock frequency is lowered to reduce power consumption, then power consumption decreases, but latency increases and performance degrades

Engineering Contradiction:
Improvepower consumptionVSAvoidlatency
Core Design Contradiction:
Use of energy by stationary objectVSLoss of time

Solution Approach 1:

The interconnect is divided into multiple independent ring buses instead of using a single shared bus or crossbar. Each ring bus can be independently activated or deactivated based on bandwidth requirements, allowing the system to segment power consumption across multiple smaller units and activate only the necessary portions.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system dynamically activates or deactivates specific ring buses based on real-time bandwidth requirements. This dynamic configuration allows the interconnect to adapt its power consumption and routing paths according to actual traffic demands, optimizing the trade-off between power efficiency and performance.

Inventive Principle:
Principle #15Dynamics

2Productivity

If multiple parallel ring buses are employed to achieve desired bandwidth, then throughput increases, but power consumption increases

Engineering Contradiction:
ImprovebandwidthVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by stationary object

Solution Approach 1:

Instead of activating all parallel ring buses continuously, the system activates only the necessary number of ring buses required to meet the current bandwidth demands. This partial action approach provides the desired throughput while avoiding the excessive power consumption that would result from keeping all buses active.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The system changes the operational parameters of the ring buses by dynamically adjusting which buses are active based on bandwidth requirements. This parameter change allows the system to scale power consumption proportionally with actual throughput needs rather than maintaining fixed high-performance configuration.

Inventive Principle:
Principle #35Parameter changes

3Adaptability or versatility

If the number of ring bus nodes increases to provide more entry and exit points, then connectivity improves, but latency of point-to-point communications increases

Engineering Contradiction:
ImproveconnectivityVSAvoidlatency
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The large ring bus is segmented into multiple smaller ring buses, each with fewer nodes. This segmentation reduces the number of nodes any single message must traverse, thereby reducing latency while maintaining overall system connectivity through the inter-ring router network.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Inter-ring routers act as intermediaries that enable direct routing between different ring buses. This intermediary structure allows messages to jump between rings rather than traversing the entire perimeter of a large ring, significantly reducing communication latency while maintaining system-wide connectivity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentEP2909730B1Processor-based hybrid ring bus interconnect
Publication Date: 2017.08.16 QUALCOMM INC
  • EP2909730B1 patent drawingFigure 1
  • EP2909730B1 patent drawingFigure 2
  • EP2909730B1 patent drawingFigure 3A~3B

AI summary

Processor-based system hybrid ring bus interconnects, and related devices, systems, and methods are disclosed. In one embodiment, a processor-based system hybrid ring bus interconnect is provided. The processor-based system hybrid ring bus interconnect includes multiple ring buses, each having a bus width and configured to receive bus transaction messages from a requester device(s). The processor-based system hybrid ring bus interconnect also includes an inter-ring router(s) coupled to the ring buses. The inter-ring router(s) is configured to dynamically direct bus transaction messages among the ring buses based on bandwidth requirements of the requester device(s). Thus, less power is consumed than by a crossbar interconnect due to simpler switching configurations. Further, the inter-ring router(s) allows for provision of multiple ring buses that can be dynamically activated and deactivated based on bandwidth requirements. This provides conservation of power when full bandwidth requirements on the processor-based system hybrid ring bus interconnect are not required.