Hybrid Ring PLL with Parallel Tuning Paths for Low Phase Jitter
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Solution Overview
Problem
Purely digital PLLs suffer from high phase jitter due to quantized phase error correction, while purely analog PLLs have complex correction paths and large footprints, and hybrid LC tank PLLs are costly and large, making them unsuitable for all applications.
Innovation Solution
A hybrid ring PLL circuit with both digital and analog paths that simultaneously control the frequency of a ring oscillator, using a digital path for discrete frequency control and an analog path for continuous frequency control, reducing phase jitter while maintaining a smaller footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a purely digital PLL is used, then the device complexity and footprint are reduced, but the phase jitter increases due to quantized phase error correction
Solution Approach 1:
The patent combines digital and analog correction paths within a single PLL circuit. The digital path provides coarse frequency adjustment with simple logic, while the analog path provides fine frequency adjustment with continuous control, merging the advantages of both approaches to reduce phase jitter while maintaining compact size.
Solution Approach 2:
The correction mechanism is segmented into two independent parallel paths: a digital correction path for integer frequency adjustments and an analog correction path for fractional frequency adjustments. This segmentation allows each path to optimize for its specific function, reducing overall phase jitter.
2Reliability
If a purely analog PLL is used, then the phase jitter is reduced due to continuous phase error correction, but the device complexity and footprint increase
Solution Approach 1:
The correction mechanism is segmented into two independent parallel paths: a digital correction path for integer frequency adjustments and an analog correction path for fractional frequency adjustments. This segmentation allows each path to optimize for its specific function, reducing overall phase jitter.
Solution Approach 2:
Instead of using a full analog correction path that would provide continuous control across the entire frequency range, the patent applies analog correction only for fine fractional adjustments, while digital correction handles the bulk of frequency tuning. This partial analog action reduces phase jitter without requiring a complete analog redesign.
3Reliability
If a hybrid LC tank PLL is used, then the phase jitter is reduced, but the cost and device footprint increase making it unsuitable for all applications
Solution Approach 1:
The patent combines digital and analog correction paths within a single PLL circuit. The digital path provides coarse frequency adjustment with simple logic, while the analog path provides fine frequency adjustment with continuous control, merging the advantages of both approaches to reduce phase jitter while maintaining compact size.
Solution Approach 2:
The patent applies analog correction only where needed - in the fine-tuning portion of the frequency control range - rather than throughout the entire system. This localized analog intervention reduces phase jitter at critical points without requiring a complete analog redesign of the entire PLL.
Data Source
AI summary
A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator.