Hybrid Cell Row Height Layout for Reliable Integrated Circuits
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Solution Overview
Problem
The gate oxide breakdown in integrated circuits affects performance and reliability, and existing designs with single cell row height architectures result in large area overhead and poor cell performance due to pin cap issues.
Innovation Solution
Implementing a mixed cell row height architecture (MCRHA) where shadow logic circuits are arranged in reduced height cell rows, with main logic circuits in normal height rows, and redundant transistors are inserted to maintain circuit operations in case of transistor failure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single cell row height architecture is used, then the layout is simple, but the area overhead is large and cell performance is poor
Solution Approach 1:
The cell row is segmented into two distinct height regions: a first cell row height for shadow logic circuits and a second cell row height for main logic circuits. This segmentation allows each region to be optimized independently, reducing overall area overhead while maintaining layout manageability through clear functional separation.
Solution Approach 2:
Different regions of the cell row are assigned different heights based on their functional requirements. The shadow logic region uses a first height optimized for its specific needs, while the main logic region uses a second height, allowing each local area to have the quality (height) most suitable for its function rather than using a uniform height throughout.
2Reliability
If redundant transistors are inserted for reliability, then circuit functionality is maintained during transistor failure, but device complexity increases
Solution Approach 1:
The shadow logic circuit is merged with the main logic circuit such that they share the same physical space and resources. The shadow logic, implemented with redundant transistors, is combined with the main logic in a unified cell structure, allowing the redundant elements to be integrated rather than added as separate components, thus limiting the increase in device complexity.
3Area of stationary object
If shadow logic circuits are placed in reduced height rows, then area overhead is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The different row heights are predetermined and designed into the cell structure before fabrication. The first cell row height and second cell row height are established as fixed design parameters, allowing manufacturing processes to target these pre-defined dimensions rather than requiring dynamic adjustment, thus managing precision requirements through upfront design specification.
Data Source
AI summary
An integrated circuit includes a first cell and a second cell. The first cell has a first height along a first direction. The second cell has a second height shorter than the first height along the first direction. A transistor of the first cell and a transistor of the second cell share a first active area, and a first boundary of the first cell, a first boundary of the second cell, a second boundary of the first cell and a second boundary of the second cell are arranged in order along the first direction.