Hybrid Row Activation Tracking for DRAM Row Hammer Mitigation

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Solution Overview

Problem

The increasing severity of row hammer interference in DRAM due to relentless scaling poses a reliability and security threat, necessitating effective mitigation strategies that are efficient and scalable for future systems.

Innovation Solution

A hybrid tracker system combining SRAM-based group-count tables and DRAM-based per-row trackers to monitor and mitigate row hammer effects, utilizing SRAM for efficient counting and DRAM for precise tracking of high-activation rows, with performance optimizations through caching.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If per-row tracking is implemented for all rows, then row hammer mitigation precision is improved, but resource overhead and performance penalty increase significantly

Engineering Contradiction:
Improverow hammer tracking precisionVSAvoidtracking structure overhead
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent divides the tracking structure into two segments: an SRAM-based group-count table that tracks aggregated counts for groups of rows, and a DRAM-based per-row tracker that tracks individual row counts. This segmentation allows the system to achieve precise per-row tracking only when necessary, while using less resource-intensive group-level tracking for the majority of rows, thereby reducing overall resource overhead while maintaining mitigation precision.

Inventive Principle:
Principle #1Segmentation

2Speed

If SRAM is used for all tracking, then access speed is improved, but area and cost increase significantly

Engineering Contradiction:
Improvetracking access speedVSAvoidtracking structure area
Core Design Contradiction:
SpeedVSArea of stationary object

Solution Approach 1:

The patent applies different memory technologies to different tracking needs: SRAM is used for the group-count table where fast access is critical for filtering the majority of rows, while DRAM is used for the per-row tracker where larger capacity is needed but access speed requirements are lower. This local differentiation of memory quality optimizes the balance between access speed and area utilization.

Inventive Principle:
Principle #3Local quality

3Reliability

If tracking threshold is reduced to address future row hammer severity, then mitigation effectiveness is improved, but false positives and performance overhead increase

Engineering Contradiction:
Improvemitigation effectivenessVSAvoidsystem performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent performs preliminary filtering using the SRAM-based group-count table before detailed per-row tracking. By first identifying groups of rows that exceed aggregation thresholds, the system can then apply more intensive per-row tracking only to those specific groups, thereby reducing false positives and performance overhead while maintaining effectiveness against future row hammer attacks with lower thresholds.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12498859B2Systems and method for tracking activations to perform row hammer mitigation in memory modules
Publication Date: 2025.12.16 GEORGIA TECH RES CORP
  • US12498859B2 patent drawing
  • US12498859B2 patent drawing
  • US12498859B2 patent drawing

AI summary

A hybrid tracker system and method are disclosed for RH mitigation, which combines the best of both SRAM and DRAM to enable low-cost mitigation of RH at ultra-low thresholds. The system consists of two structures. First, an SRAM-based structure is provided that tracks aggregated counts at the granularity of a group of rows and is sufficient for the vast majority of rows, which receive only a few activations. Second, a per-row tracker stored in the DRAM-array is provided which can track an arbitrary number of rows; however, to limit performance overheads, this tracker is used only for the small number of rows that exceed the tracking capability of the SRAM-based structure.