Hybrid Interconnect Structure Using Ru and Cu for Lower Resistance
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Solution Overview
Problem
Semiconductor devices face challenges in achieving high reliability and speed due to limitations in connection line resistance and complexity, particularly in the integration of different metal layers with varying widths and aspect ratios.
Innovation Solution
The semiconductor device incorporates a hybrid connection line structure with a first metal layer of ruthenium (Ru) and a second metal layer of copper (Cu), where the second metal layer surrounds the ruthenium to minimize costs and eliminate separate CMP processes, improving resistance and operating speed by varying metal layer resistance based on width.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single metal layer is used for connection lines, then the fabrication process is simple, but the resistance cannot be optimized for different width requirements
Solution Approach 1:
The patent applies local quality by using different metal materials (first metal and second metal) in different regions of the connection line structure. The first metal layer is used for wider connection lines where lower resistance is critical, while the second metal layer is used for narrower connection lines where process compatibility and cost are more important. This localized material differentiation optimizes resistance characteristics for each specific width requirement without requiring a completely complex multi-layer structure throughout.
Solution Approach 2:
The patent employs composite materials by combining first metal and second metal layers in a hybrid connection line structure. The first metal layer (e.g., copper) provides low resistance for wide lines, while the second metal layer (e.g., cobalt or tungsten) provides compatibility with existing fabrication processes for narrow lines. This composite approach allows the connection line system to achieve optimized electrical performance across different width scenarios while maintaining processability.
2Reliability
If different metal layers with varying widths are integrated, then resistance can be optimized, but the fabrication complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the connection line structure into distinct first metal layer and second metal layer components. Each layer can be fabricated with different width characteristics optimized for their specific function. The first metal layer is segmented to provide wider pathways for high-current paths, while the second metal layer is segmented for narrower connections requiring different electrical characteristics. This segmentation allows independent optimization of each layer's width and material properties.
Solution Approach 2:
The patent utilizes parameter changes by varying both the material composition and width parameters of different metal layers. The first metal layer uses materials with lower resistance and wider dimensions for speed-critical paths, while the second metal layer uses materials compatible with standard fabrication processes and narrower dimensions for other connections. This parameter differentiation enables resistance and speed optimization without requiring complete process redesign.
3Reliability
If wider connection lines are used, then resistance decreases, but the aspect ratio varies requiring separate CMP processes
Solution Approach 1:
The patent applies merging by combining the first metal layer and second metal layer into a unified hybrid connection line structure that can be fabricated using a single CMP (chemical mechanical polishing) process. Instead of separately planarizing different metal layers with different aspect ratios, the hybrid structure allows both metal types to be integrated in one CMP step, reducing the number of process steps and associated complexity while still achieving the desired resistance characteristics through material and width selection.
Data Source
AI summary
A semiconductor device includes an interlayer dielectric layer on a substrate, a first connection line that fills a first trench of the interlayer dielectric layer, the first trench having a first width, and a second connection line that fills a second trench of the interlayer dielectric layer, the second trench having a second width greater than the first width, and the second connection line including a first metal layer that covers an inner sidewall of the second trench, a barrier layer that covers a bottom surface of the second trench, and a second metal layer on the first metal layer and the barrier layer, the first connection line and the first metal layer include a first metal, and the second metal layer includes a second metal different from the first metal.