Hybrid Satellite Processor with Dynamic Bandwidth Allocation
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Solution Overview
Problem
Current multi-beam satellite communication systems face challenges in providing efficient, flexible, and low-latency connectivity due to limitations in switching capabilities, resource handling, and the need for frequent updates to accommodate evolving air interfaces, leading to increased mass, power consumption, and complexity.
Innovation Solution
A hybrid processor system for multi-beam satellites that combines a burst switching processor with an on-board processor controller, utilizing a five-stage Clos switching network and software-defined radio management to enable dynamic bandwidth allocation, non-blocking switching, and reconfigurability, supporting multiple frame durations and standards evolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If regenerative satellite architectures are used to achieve high flexibility and reduced delay, then switching capabilities and resource handling flexibility are improved, but implementation complexity and payload mass increase
Solution Approach 1:
The satellite payload is segmented into transparent processing units that handle switching and routing functions independently, avoiding the need for complex regenerative processing across the entire system. Each transparent processor handles specific traffic flows with dedicated switching logic.
Solution Approach 2:
A ground-based network control center acts as an intermediary, managing the complex switching logic and resource allocation externally. The satellite payload receives simplified control commands and executes predetermined switching patterns, reducing on-board complexity while maintaining flexibility.
2Device complexity
If transparent satellite architectures are used to achieve broadband connectivity with affordable complexity, then device complexity is reduced, but switching flexibility and resource handling capabilities are limited
Solution Approach 1:
The transparent satellite architecture incorporates dynamic switching capabilities that can be reconfigured in real-time based on traffic demands. The switching fabric allows dynamic allocation of bandwidth and routing paths while maintaining the simplicity of transparent processing.
Solution Approach 2:
The transparent processor is designed with universal switching logic that can handle multiple traffic types, protocols, and routing scenarios through a single unified architecture. This multi-functional capability provides resource handling flexibility without increasing hardware complexity.
3Productivity
If deterministic switching with predefined resource allocations is used, then switching capacity for predictable traffic is improved, but adaptability to unpredictable traffic patterns deteriorates
Solution Approach 1:
The system performs preliminary setup of switching paths and resource allocations based on predicted traffic patterns. The ground control center pre-configures routing tables and bandwidth allocations for expected traffic flows, enabling fast deterministic switching for predictable scenarios.
Solution Approach 2:
The switching system incorporates feedback mechanisms that monitor actual traffic patterns and dynamically adjust resource allocations. When unpredictable traffic patterns are detected, the system adapts by reconfiguring switching paths and bandwidth assignments in real-time based on observed demands.
Data Source
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AI summary
The invention concerns a hybrid processor system (1) for use on board a telecommunications multi-beam satellite, that is controllable by a network control centre via one or more control channels and is designed to link ground terminals by: providing uplink and downlink traffic channels on several satellite beams; routing atomic switched information blocks from the uplink traffic channels to the downlink traffic channels; and exchanging signaling data with the ground terminals on one or more uplink signaling channels and one or more downlink signaling channels. All the atomic switched information blocks have one and the same given time duration and one and the same given baseband bandwidth. Each uplink traffic channel has a respective uplink bandwidth including respective uplink frequencies, and carries, at said respective uplink frequencies, respective atomic switched information blocks in respective uplink time slots organized into respective uplink time frames forming respective uplink time superframes. Each downlink traffic channel has a respective downlink bandwidth including respective downlink frequencies, and carries, at said respective downlink frequencies, respective atomic switched information blocks in respective downlink time slots organized into respective downlink time frames forming respective downlink time superframes. The hybrid processor system (1) comprises a burst switching processor (11), and an on-board processor controller (12), which is configured to store service information items indicative of: said given time duration and said given baseband bandwidth of the atomic switched information blocks; the respective uplink bandwidth, the respective uplink frequencies, a respective time length of the respective uplink time slots, and respective structure features of the respective uplink time frames and superframes of each uplink channel; the respective downlink bandwidth, the respective downlink frequencies, a respective time length of the respective downlink time slots, and respective structure features of the respective downlink time frames and superframes of each downlink channel; and quality of service and priority rules for serving the ground terminals. The on-board processor controller (12) is further configured to extract, from incoming signaling data received on the uplink signaling channel(s), capacity requests sent by the ground terminals, wherein the capacity requests are extracted by the on-board processor controller (12) by demodulating and decoding the incoming signaling data. Moreover, the on-board processor controller (12) is also configured to assign to each pair or set of ground terminals to be linked respective frequency, space and time resources on the basis of the stored service information items and of all the capacity requests received from the ground terminals, wherein said respective frequency, space and time resources includes: one or more respective uplink frequencies of one or more respective uplink channels provided on one or more respective satellite beams; one or more respective uplink time slots in one or more respective uplink time frames in one or more uplink time superframes of said one or more respective uplink channels; one or more respective downlink frequencies of one or more respective downlink channels provided on said one or more respective satellite beams; and one or more respective downlink time slots in one or more respective downlink time frames in one or more downlink time superframes of said one or more respective downlink channels. Additionally, the on-board processor controller (12) is further configured to: generate resource assignment messages indicative of the frequency and time resources assigned to the ground terminals; generate outgoing signaling data to be transmitted to the ground terminals on the downlink signaling channel(s), wherein the outgoing signaling data are generated by the on-board processor controller (12) by encoding and modulating the resource assignment messages; generate a routing map on the basis of the frequency, space and time resources assigned to the ground terminals; generate switching commands based on the routing map; extract, from control data received on the control channel(s), control messages sent by the network control centre, wherein the control messages are extracted by the on-board processor controller (12) by demodulating, decoding and decrypting the control data; and update the stored service information items on the basis of the control messages. The burst switching processor (11) is configured to route the atomic switched information blocks on the basis of the switching commands generated by the on-board processor controller (12). Whereby: the on-board processor controller (12) is configured to operate in a regenerative way with respect to the signaling data, and is reconfigurable by the network control centre; and the burst switching processor (11) is configured to operate in a digital transparent way with respect to the atomic switched information blocks, and is operable by the on-board processor controller (12) to route the atomic switched information blocks in frequency, space and time domains.