Hybrid Scan Chains Using Latches for Low-Cost Memory Array Testing
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Solution Overview
Problem
Conventional scan chains using scannable flip-flops are too expensive for large memory arrays in integrated circuits, making scan testing unfeasible, and existing latch-based architectures lack a cost-effective solution for enabling scan testing in memory arrays.
Innovation Solution
The development of low-cost scan chain architectures using scannable latches, which utilize a sequence of non-overlapping sub-clock pulses to ripple data through latches one position at a time, allowing for efficient scan testing of large memory arrays with minimal transistor count.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional scan chains using scannable flip-flops are used, then scan testing capability is achieved, but the cost becomes too high for large memory arrays
Solution Approach 1:
The patent replaces expensive scannable flip-flops with cheaper scannable latches that have fewer transistors. The latches are designed to be functional but less complex than flip-flops, reducing the transistor count from typically 18-24 transistors per flip-flop to 6-10 transistors per latch, making scan testing economically viable for large memory arrays
Solution Approach 2:
The patent changes the fundamental parameter of the storage element from flip-flop to latch, which alters the transistor count and cost characteristics. Additionally, it introduces non-overlapping clock signals with specific timing relationships to control the latches, changing the temporal parameters of operation to enable scan functionality in latch-based memory arrays
2Device complexity
If latch-based architectures are used, then cost is reduced, but existing architectures lack a cost-effective solution for enabling scan testing
Solution Approach 1:
The patent segments the memory array into rows and columns with dedicated scan paths. Each row or column can be independently scanned using latches, allowing scan testing to be performed on segments rather than requiring the entire array to use expensive flip-flops. This segmentation enables cost-effective scan testing by applying the latch-based approach selectively to memory structures
Solution Approach 2:
The patent introduces scan-specific control logic and non-overlapping clock signal generators as intermediary elements that enable scan testing functionality in latch-based architectures. These intermediary components coordinate the latches to perform scan operations without requiring the latches themselves to be as complex as flip-flops, thus maintaining cost-effectiveness while achieving scan capability
Data Source
AI summary
An electronic circuit features a hybrid scan chain design comprising a flip-flop-based part of the scan chain and a latch-based part of the scan chain. The latch-based part may be included in an array of memory cells and includes one or more chain segments of storage memory cells. Chain segments are separated by chain buffer memory cells. Memory cells of each chain segment are coupled with a sequence generator that generates a sequence of non-overlapping pulses from a pulse in a scan clock (SCLK) signal. The circuit includes a memory element interfacing the scan out (SO) output of the flip-flop-based scan chain with the scan in (SI) input of the latch-based scan chain. The memory element captures and retains the value of the final flip-flop in the flip-flop-based scan chain, enabling subsequent access by the initial latch in the latch-based scan chain without loss of data.