Hybrid Seed Layer Layout for Uniform Plating and Inductor Impedance
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Solution Overview
Problem
There is a tradeoff between using a low sheet resistance seed layer for uniform deposition of conductive material across large areas and a high sheet resistance seed layer that improves the operation of inductors, particularly in areas where magnetic material is to be deposited, as low sheet resistance can undermine the efficiency of inductors by lowering impedance.
Innovation Solution
Implementing a hybrid seed layer architecture with high resistivity material in regions where magnetic material is to be deposited and low resistivity material elsewhere, ensuring uniform deposition across large areas while maintaining inductor efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a low sheet resistance seed layer is used, then uniform deposition of conductive material across large areas is achieved, but inductor efficiency deteriorates due to lowered impedance
Solution Approach 1:
The patent applies local quality by implementing different seed layer resistivity characteristics in different spatial regions of the substrate. Specifically, high resistivity seed layers are used in regions where magnetic material is deposited (to maintain inductor efficiency), while low resistivity seed layers are used in other regions (to enable uniform deposition of conductive material). This regional differentiation resolves the contradiction by allowing each region to have the seed layer properties optimized for its specific function.
Solution Approach 2:
The patent segments the seed layer into multiple regions with different electrical resistivity characteristics. Rather than using a uniform seed layer across the entire substrate, the seed layer is divided into functionally distinct zones: one zone with high resistivity for inductor regions and another zone with low resistivity for general conductive material deposition. This segmentation allows simultaneous optimization of both inductor efficiency and deposition uniformity in different areas.
2Reliability
If a high sheet resistance seed layer is used, then inductor efficiency is improved by maintaining impedance, but uniform deposition of conductive material across large areas deteriorates
Solution Approach 1:
The patent implements local quality by assigning different electrical resistivity properties to different spatial regions of the seed layer. High resistivity is localized to regions where magnetic material and inductors are present, preserving impedance and inductor efficiency. Low resistivity is localized to other regions where uniform deposition of conductive material is the primary requirement. This localized property assignment resolves the contradiction between inductor efficiency and deposition uniformity.
Solution Approach 2:
The seed layer is segmented into multiple functional regions with distinct electrical characteristics. One segment has high sheet resistance optimized for inductor performance, while another segment has low sheet resistance optimized for uniform electroplating. This segmentation enables each region to independently optimize for its specific function without compromising the other.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The hybrid seed layer architecture facilitates uniform deposition of conductive material across large areas while enhancing the efficiency of inductors by minimizing impedance issues.
Implementation Method 1
In semiconductor device fabrication, layers of metal are often deposited on an underlying substrate using electroplating (also known as electrolytic plating or e-lytic plating)
Implementation Method 2
Processes other than electroplating that can be used to deposit a metal seed layer include chemodeposition processes (e.g., electroless or e-less plating), physical vapor deposition (PVD), sputtering, and chemical vapor deposition
Data Source
AI summary
Metal seed layers with different sheet resistances in integrated circuit packages are disclosed. An integrated circuit package includes: a substrate having a first surface and a second surface opposite the first surface, and a first seed layer on a sidewall of an opening in the substrate. The opening is to extend from the first surface toward the second surface. The integrated circuit package also includes a second seed layer on the first surface of the substrate. The second seed layer is spaced apart from the opening.