Hybrid Semiconductor Circuits via Cavity Epitaxy
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The integration of compound semiconductors with silicon substrates is hindered by lattice mismatch, thermal expansion coefficient mismatch, and structural mismatch, making it challenging to achieve high crystalline quality and efficient fabrication of hybrid semiconductor circuits.
Innovation Solution
A method involving the formation of an insulating layer with a cavity structure on a semiconductor substrate, allowing for the growth of a semiconductor filling structure with a different material, which serves as a seed surface for the second semiconductor device, enabling precise alignment and fabrication of hybrid circuits with III-V compound materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If direct epitaxy of blanket layers is used to achieve gradual lattice transition, then defect density is reduced, but relatively thick transition layers are needed which increases device complexity
Solution Approach 1:
The patent divides the transition structure into discrete cavity features with controlled dimensions rather than using a continuous thick transition layer. The cavities are formed as separate entities within the insulating layer, allowing the lattice transition to occur through controlled epitaxial growth within each cavity rather than through a thick blanket transition layer.
Solution Approach 2:
The patent applies different structural approaches in different regions: the insulating layer provides electrical isolation in certain areas, while the cavity structures provide controlled lattice transition zones in specific locations. This localized approach allows crystalline quality to be improved where needed without unnecessarily increasing overall device complexity.
2Adaptability or versatility
If bonding techniques are used to combine compound semiconductors with silicon wafers, then integration is achieved, but the process becomes expensive and limited to small wafer sizes
Solution Approach 1:
The patent merges the insulating layer formation with the cavity structure creation in a single integrated process. The cavities are formed within the insulating layer using the same patterning and etching steps, eliminating the need for separate bonding processes and enabling scalability to larger wafer sizes.
Solution Approach 2:
The insulating layer serves multiple functions: it provides electrical isolation between devices and simultaneously serves as the matrix in which the cavity structures are formed. This multi-functionality simplifies the overall fabrication process and removes the need for additional bonding steps required by other integration techniques.
3Reliability
If aspect ratio trapping is used to terminate crystalline defects, then defect propagation is reduced, but the technique requires non-crystalline sidewalls which complicates the structure
Solution Approach 1:
The cavity structures act as intermediary elements that terminate defect propagation paths. Rather than relying on non-crystalline sidewalls, the cavities provide a physical barrier within the crystalline structure that stops defect propagation while maintaining overall structural simplicity and compatibility with standard fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach facilitates efficient and precise fabrication of hybrid semiconductor circuits with different semiconductor materials, achieving high crystalline quality and enabling the integration of III-V compound semiconductors on silicon substrates, suitable for advanced devices like sub-10 nm geometry FETs and photonic devices.
Implementation Method 1
growing via the opening from the seed surface a semiconductor filling structure comprising a second semiconductor material different from the first semiconductor material in the growth channel
Data Source
AI summary
A method is disclosed for fabricating a semiconductor circuit. A semiconductor substrate is provided. A first semiconductor device is fabricated including a first semiconductor material on the substrate and forming an insulating layer including a cavity structure on the first semiconductor device. The cavity structure includes at least one growth channel and the growth channel connects a crystalline seed surface of the first semiconductor device with an opening. Further steps include growing via the opening from the seed surface a semiconductor filling structure including a second semiconductor material different from the first semiconductor material in the growth channel, forming a semiconductor starting structure for a second semiconductor device from the filling structure, and fabricating a second semiconductor device including the starting structure. Corresponding semiconductor circuits are also disclosed.