Hybrid-Shared Switch Architecture for High-Bandwidth Traffic Management
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Solution Overview
Problem
Current network switch architectures face challenges in scaling operating clock frequency to achieve high bandwidth without increasing power consumption and complexity, particularly in supporting more and faster ports, and they struggle with efficient memory sharing and buffering due to limitations in shared-buffer and input-output-buffered architectures.
Innovation Solution
The hybrid-shared switch architecture combines elements of shared-buffer and input-output-buffered architectures, utilizing a small number of large ingress buffers to achieve high buffer sharing among input ports, with a centralized scheduler managing traffic across all ingress buffers to maximize bandwidth and ensure all output ports are satisfied, while using a read launcher to resolve buffer bank conflicts and allow out-of-order reads to prevent stalling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If shared-buffer architecture is used to achieve high buffer sharing among input ports, then bandwidth utilization is improved, but memory access conflicts and stalling increase
Solution Approach 1:
The patent segments the shared buffer into multiple independent buffer banks, where each bank can be accessed independently by different input ports. This segmentation reduces memory access conflicts because multiple ports can simultaneously access different banks without interfering with each other, while still maintaining high buffer sharing ratios across the system.
Solution Approach 2:
The patent introduces a new dimension of organization by mapping input ports to buffer banks through a dimensional mapping scheme. Instead of single-port access to a unified buffer, the system creates a multi-dimensional access structure where ports are distributed across buffer banks, enabling parallel access along the bank dimension while maintaining logical buffer sharing.
2Productivity
If input-output-buffered architecture is used to reduce buffer sharing conflicts, then memory access efficiency is improved, but bandwidth requirements on ingress buffers increase
Solution Approach 1:
The patent applies local quality by giving each input port dedicated access to specific buffer banks rather than requiring all ports to access the entire buffer. This localized access pattern improves memory access efficiency for each port while reducing the aggregate bandwidth requirements on ingress buffers, as each port only needs to handle traffic to its assigned banks.
Solution Approach 2:
The patent implements partial buffer sharing where input ports have priority access to specific buffer banks rather than full sharing across all banks. This partial action approach maintains sufficient buffer sharing for high productivity while avoiding the excessive bandwidth requirements that would result from complete buffer sharing across all ports.
3Speed
If operating clock frequency is scaled up to achieve high bandwidth, then data transmission speed is improved, but power consumption and complexity increase
Solution Approach 1:
The patent implements dynamic buffer bank allocation where input ports can dynamically access different buffer banks based on traffic patterns rather than being statically assigned. This dynamic approach allows the system to achieve high data transmission speeds through efficient parallel access without requiring uniformly high clock frequencies across all buffer access paths, thereby reducing overall power consumption.
4Adaptability or versatility
If more input ports are added to increase capacity, then network connectivity is improved, but buffer sharing efficiency and complexity deteriorate
Solution Approach 1:
The patent segments the buffer system into multiple banks that can be independently managed, allowing the addition of more input ports without proportionally increasing buffer sharing complexity. Each new port can be mapped to existing buffer banks, and the segmented structure naturally handles the increased connectivity requirements while maintaining efficient sharing ratios through the modular bank architecture.
Data Source
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AI summary
In the subject system for a network switch may receive one or more packets via a set of input ports. The network switch may write the one or more packets into an ingress buffer of an ingress tile shared by the set of input ports. The network switch may read the one or more packets from the ingress buffer according to a schedule by a scheduler. The network switch may forward the read one or more packets to a plurality of output ports.