Hybrid SiC Wafer Structure for High-Defect Drift Layers

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Solution Overview

Problem

The existing process for creating silicon carbide (SiC) wafers results in high lattice defect density (hLDD), leading to yield loss and increased costs due to the need to slow down processing to reduce defect production, making unusable wafers and requiring remelting and recycling.

Innovation Solution

Utilizing hLDD SiC substrate wafers with inherent defects as a base drift layer for hybrid wafers, incorporating a device layer such as silicon or gallium nitride, and optionally a buffer layer of polycrystalline or amorphous SiC to buffer stress and create hybrid wafers that can be processed faster, reducing costs and increasing yield.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the SiC ingot growth and wafer processing speed is increased, then productivity is improved, but the lattice defect density increases leading to yield loss

Engineering Contradiction:
Improveprocessing speedVSAvoiddefect density
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The wafer is segmented into distinct functional layers: a base drift layer made from hLDD SiC substrate wafer and a device layer made from low-defect semiconductor material. This segmentation allows each layer to serve its specific purpose - the base drift layer provides high-voltage handling and thermal conductivity, while the device layer provides low-defect device fabrication.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention creates a hybrid wafer structure combining two different semiconductor materials - hLDD SiC and a low-defect semiconductor material (such as 4H-SiC, 3C-SiC, Si, or GaN). This composite structure leverages the advantages of both materials: the hLDD SiC provides thermal management and high-voltage blocking, while the low-defect material provides reliable device operation.

Inventive Principle:
Principle #40Composite materials

2Reliability

If slower processing is used to reduce hLDD wafer production, then defect density is reduced, but productivity and manufacturing cost are worsened

Engineering Contradiction:
Improvedefect densityVSAvoidmanufacturing cost
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The invention converts the harmful effect of hLDD SiC substrate wafers (which were previously considered defective and unusable) into a beneficial base drift layer. The high lattice defects in the SiC substrate are acceptable when used as the base drift layer, as the critical device fabrication occurs in the separate low-defect device layer. This transforms waste material into a functional component.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Solution Approach 2:

The invention changes the acceptable parameter range for the base drift layer by accepting high lattice defect density (hLDD) for SiC substrate wafers, while maintaining low defect density requirements for the device layer. This parameter differentiation allows faster processing for the base drift layer production without compromising overall device quality.

Inventive Principle:
Principle #35Parameter changes

3Productivity

If hLDD SiC substrate wafers are used directly for device fabrication, then productivity is improved, but device reliability is worsened due to defects

Engineering Contradiction:
Improvewafer utilizationVSAvoiddevice functionality
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The wafer is segmented into distinct functional layers: a base drift layer made from hLDD SiC substrate wafer and a device layer made from low-defect semiconductor material. This segmentation allows each layer to serve its specific purpose - the base drift layer provides high-voltage handling and thermal conductivity, while the device layer provides low-defect device fabrication.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different quality requirements are applied to different regions of the wafer structure. The base drift layer accepts high lattice defect density since it primarily handles thermal management and voltage blocking, while the device layer maintains low defect density to ensure reliable device operation. This local quality differentiation optimizes both productivity and device reliability.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The hybrid wafers enable faster processing and utilization of otherwise unusable hLDD SiC substrate wafers, improving thermal conductivity and enabling device switching in low-defect semiconductor materials while handling high voltages, thus reducing production costs and increasing yield.

Implementation Method 1

High-purity silicon powder and high-purity carbon powder are used to grow SiC single crystals by physical vapor transport (PVT) to form the boule

Methodology Applied
Scientific EffectPhysical vapor transport: Physical Vapour Deposition

Implementation Method 2

growing by deposition a silicon carbide (SiC) ingot

Methodology Applied
Scientific EffectDeposition: Deposition (physical)

Data Source

PatentUS20250290224A1HIGH DEFECT SiC WAFER WITH DEVICE LAYER AND METHODS OF MANUFACTURE
Publication Date: 2025.09.18 MICROCHIP TECHNOLOGY INC
  • US20250290224A1 patent drawing
  • US20250290224A1 patent drawing
  • US20250290224A1 patent drawing

AI summary

Aspects provide forming hLDD SiC substrate wafers having a number of defects per square centimeter in excess of a predetermined threshold, and using the hLDD SiC substrate wafers to make vertical diffused metal oxide semiconductor (DMOS) field effect transistors (FET). In particular, methods comprise: growing by deposition a SiC ingot; slicing the SiC ingot to produce a plurality of base drift wafers; identifying base drift wafers having a number of defects per square centimeter in excess of a predetermined threshold; and forming a respective device layer on the identified base drift wafers. An aspect provides a DMOS FET having a base drift layer on the device layer and comprising SiC and having a number of defects per square centimeter in excess of a predetermined threshold.