Hybrid Silicon Array Substrate for Micro LED Displays
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Solution Overview
Problem
Existing technologies face challenges in simultaneously applying amorphous silicon and polycrystalline silicon in Micro LED displays, limiting electron mobility and practicality for large-generation panels.
Innovation Solution
An array substrate is designed with a first silicon layer composed of polycrystalline silicon under the channel and amorphous silicon elsewhere, combined with additional amorphous silicon layers, and an etching barrier layer, fabricated using laser annealing to enhance electron mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If amorphous silicon is used for the active layer, then the manufacturing process is simple and suitable for large-generation panels, but the electron mobility is low (0.5 cm2/Vs) and insufficient for current driving
Solution Approach 1:
The patent applies local quality by creating different silicon phases in different regions of the active layer. The portion under the channel is converted to polycrystalline silicon via laser annealing to achieve high electron mobility, while the source and drain regions remain as amorphous silicon to maintain simple manufacturing and good interface characteristics. This spatial differentiation resolves the contradiction between manufacturing simplicity and electron mobility requirements.
2Reliability
If polycrystalline silicon is used for the active layer, then the electron mobility is high (up to 100 cm2/Vs), but the structure becomes complex and film uniformity is poor, limiting application in generation panels
Solution Approach 1:
The patent uses local quality to convert only the channel region to polycrystalline silicon through selective laser annealing, while keeping the source and drain regions as amorphous silicon. This localized approach achieves high electron mobility where needed without the complexity and uniformity issues of fully polycrystalline structures, enabling practical application in generation panels.
Solution Approach 2:
The active layer is segmented into different functional regions with different silicon phases: polycrystalline silicon in the channel region for high mobility and amorphous silicon in the source/drain regions for manufacturing simplicity. This segmentation allows each region to be optimized independently, resolving the contradiction between mobility and complexity.
3Ease of manufacture
If conventional silicon TFT structure is used, then the manufacturing process is simple, but the electron mobility is insufficient to provide large on-state current for current driving
Solution Approach 1:
The patent applies local quality by converting only the channel region under the source-drain electrode to polycrystalline silicon through selective laser annealing, while maintaining amorphous silicon in the source and drain regions. This creates a hybrid structure that achieves high electron mobility (and thus high on-state current) in the channel while preserving the manufacturing simplicity of amorphous silicon processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves higher electron mobility than conventional silicon TFTs, enabling the array substrate to be used in large-generation lines with improved light-emitting effects.
Implementation Method 1
performing laser annealing by a laser beam, such that the exposed amorphous silicon under the channel is converted into polycrystalline silicon
Implementation Method 2
performing laser annealing by a laser beam, such that the exposed amorphous silicon under the channel is converted into polycrystalline silicon
Data Source
AI summary
The array substrate includes: a substrate; a gate electrode; a gate insulating layer; an active layer; a source-drain electrode; a passivation layer; a pixel electrode; the active layer includes a first silicon layer, and the first silicon layer disposed below the channel is composed of polycrystalline silicon, and the remaining part of the first silicon layer is composed of amorphous silicon.