Hybrid Parallel SLC Memory Programming to Reduce Programming Time
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory devices face performance delays due to sequential programming of single-level cell (SLC) memory, which utilizes control logic for each page, leading to unwanted performance bottlenecks.
Innovation Solution
Implementing hybrid parallel programming by storing SLC data in a cache register and one or more data registers, allowing concurrent programming of multiple pages to sub-blocks within the SLC cache, utilizing control logic to perform operations in parallel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If sequential programming of SLC memory pages is used, then control logic can be simplified, but programming time increases significantly
Solution Approach 1:
The control logic is segmented into multiple independent control units (first control logic, second control logic, third control logic) that can operate in parallel. Each control unit manages a separate page buffer and programming operation, allowing simultaneous programming of multiple SLC memory pages without requiring a single complex sequential controller.
Solution Approach 2:
Data is pre-loaded into multiple page buffers (first page buffer, second page buffer, third page buffer) before programming begins. This preliminary action allows the control logic to initiate parallel programming operations immediately without sequential data transfer delays, reducing overall programming time while maintaining manageable control complexity.
2Productivity
If parallel programming operations are implemented, then programming speed increases, but control logic complexity increases
Solution Approach 1:
The control logic is divided into multiple independent control units that each manage a specific page buffer and programming operation. This segmentation allows parallel programming operations to proceed simultaneously with minimal coordination overhead, increasing programming throughput while keeping each control unit relatively simple.
Solution Approach 2:
Multiple control logic units are implemented with identical or similar functionality, each capable of independently managing page buffer operations and programming. This universality allows the system to achieve high parallel throughput through replication of simple, proven control logic rather than designing a single complex controller.
3Loss of time
If multiple page buffers are used for parallel programming, then programming performance improves, but device complexity increases
Solution Approach 1:
The memory structure is segmented into multiple independent page buffers (first page buffer, second page buffer, third page buffer), each associated with its own control logic unit. This segmentation enables parallel data loading and programming operations across multiple buffers simultaneously, reducing programming time while maintaining a modular and manageable device architecture.
Data Source
AI summary
A memory device includes a page buffer with multiple registers and a memory array, configured as single-level cell (SLC) memory, including a set of sub-blocks coupled with the page buffer. Control logic is operatively coupled with the page buffer and causes a first page of SLC data to be stored in the multiple registers. The control logic causes a subsequent page of the SLC data to be stored in the multiple registers. The control logic causes the subsequent page and the first page of the SLC data stored in the multiple registers to be concurrently programmed to the set of sub-blocks. The control logic causes at least some of the operations for programming the first page and the subsequent page to the set of sub-blocks to be performed in parallel.