Hybrid SM3 SHA Accelerator Logic Integration
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Solution Overview
Problem
Conventional hardware accelerators require separate implementations for SM3 and SHA acceleration processors, leading to significant area usage and high logic overhead due to the large number of gates required, which is inefficient and costly.
Innovation Solution
Integration of SM3 and SHA acceleration processors into a hybrid processor that combines round computation and message scheduling, reducing the total gate count and logic overhead while maintaining performance, by selectively operating in either SHA or SM3 mode for message processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate implementations of SM3 and SHA acceleration processors are used, then each algorithm can be independently optimized, but the total area usage and logic overhead increase significantly
Solution Approach 1:
The patent combines separate SM3 and SHA acceleration processors into a single hybrid processor that can execute both algorithms. The hybrid processor integrates the message scheduling units and round computation units of both algorithms into one unified structure, sharing common resources such as arithmetic logic units, registers, and control logic, thereby reducing total area usage while maintaining support for both cryptographic standards
Solution Approach 2:
The hybrid processor is designed with multi-functionality to support both SM3 and SHA algorithms through a single processing unit. It includes configurable message scheduling paths and round computation paths that can be dynamically selected based on the required algorithm, allowing one processor to perform multiple cryptographic functions without requiring separate dedicated hardware for each algorithm
2Reliability
If separate implementations of SM3 and SHA acceleration processors are used, then each algorithm has dedicated hardware, but logic overhead increases by approximately 60%
Solution Approach 1:
The patent merges the logic circuits for SM3 and SHA into a shared hybrid structure. Common logical operations such as bitwise operations, arithmetic operations, and data path routing are consolidated into shared units that can be configured for either algorithm, eliminating redundant logic and reducing overall device complexity while preserving dedicated hardware capabilities for both standards
3Area of stationary object
If a hybrid processor integrates round computation and message scheduling, then area usage reduces by 30%, but device complexity increases
Solution Approach 1:
The hybrid processor is segmented into distinct functional modules including a message scheduling unit and a round computation unit, each with dedicated control logic. This modular segmentation allows independent optimization of each function while sharing common resources, reducing area usage through resource sharing without excessive increase in overall complexity due to the structured organization of modules
Data Source
AI summary
A processing system includes a memory and a processing logic operatively coupled to the memory. The processing logic includes a message scheduling module selectively operating in one of a SHA mode or an SM3 mode to generate a sequence of message words based on an incoming message. The processing logic also includes a round computation module selectively operating in one of the SHA mode or the SM3 mode to perform at least one of a message expansion or a message compression based on at least one message word of the sequence of message words.