Hybrid SoC Die Layout for 3D Memory Heat Isolation
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Solution Overview
Problem
Existing semiconductor memory devices face thermal issues due to hotspots on system-on-chip (SoC) logic devices, which complicate cell retention time control and signal integrity, particularly in memory-intensive applications like artificial intelligence, and current 3D DRAM stacking solutions exacerbate these problems.
Innovation Solution
A hybrid SoC die structure is introduced with a wide input/output logic die area isolated from the SoC logic area, eliminating the interposer and incorporating a thermal isolation layer and control circuits to manage thermal hotspots, enhancing memory bandwidth and density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 3D DRAM stacking is implemented on SoC logic devices, then memory density and bandwidth are improved, but thermal management deteriorates due to hotspot generation
Solution Approach 1:
The die is segmented into two distinct areas: a wide IO logic die area for memory stacking and an SoC logic die area for processing functions. This segmentation allows memory stacks to be placed on the IO area while keeping the hot SoC logic area separate, thereby improving memory density without compromising thermal management of the logic area.
Solution Approach 2:
An interposer is introduced as an intermediary component between the memory stacks and the SoC logic die area. The interposer provides thermal isolation, preventing heat from the SoC logic area from affecting the memory stacks, thus enabling high-density memory integration while maintaining thermal management.
2Reliability
If memory stacks are integrated closer to SoC logic area, then signal integrity improves, but thermal interference worsens
Solution Approach 1:
The interposer serves as a thermal intermediary that physically separates the memory stacks from the hot SoC logic area while maintaining electrical connectivity. This intermediary structure preserves signal integrity through controlled interconnections while blocking thermal interference between the two areas.
Solution Approach 2:
By segmenting the die into IO logic area and SoC logic area, the patent creates distinct thermal zones. The memory stacks on the IO area can be closely integrated with the SoC logic area through the interposer, maintaining signal integrity, while the segmentation itself prevents thermal interference from propagating between areas.
3Duration of action of stationary object
If DRAM cell retention time is extended, then memory capacity improves, but thermal control complexity increases due to refresh specifications
Solution Approach 1:
The interposer provides thermal isolation that creates a stable thermal environment for DRAM cells, reducing the impact of thermal fluctuations from the SoC logic area. This stable thermal environment helps maintain consistent cell retention times, improving memory capacity while reducing the complexity of thermal control mechanisms needed to manage refresh specifications.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This structure improves thermal management, reduces performance throttling, and enhances signal integrity, supporting high memory bandwidth and density, particularly beneficial for AI applications.
Implementation Method 1
incorporating a thermal isolation layer and control circuits to manage thermal hotspots
Data Source
AI summary
A three-dimensional (3D) stacked chip package is described. The 3D stacked chip package includes a die having a wide input/output (IO) logic die area and a system-on-chip (SoC) logic die area isolated from the wide IO logic die area. The 3D stacked chip package also includes a memory stack on the wide IO logic area of the die. The 3D stacked chip package further includes a package substrate supporting the die.