Hybrid SOI Bulk MTP Cell Design for Compact Memory
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Solution Overview
Problem
Existing multiple-time programmable (MTP) memory devices on silicon-on-insulator (SOI) technology face issues with slow access time, small coupling ratio, and large cell size, along with high costs due to additional masking steps required for improvement.
Innovation Solution
A method is developed to form a compact hybrid SOI and bulk MTP cell by creating a bulk region in a SOI wafer, forming n-type and p-type wells, and constructing common floating gate stacks with shared and separate raised source/drain structures, utilizing shallow trench isolation and interlayer dielectric layers, without additional costly masking steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional masking steps are used to improve coupling ratio, then coupling ratio is improved, but manufacturing cost increases
Solution Approach 1:
The patent divides the MTP cell into two distinct regions: a bulk region with n-type well for high coupling ratio performance, and an SOI region with p-type well for cost-effective manufacturing. This spatial segmentation allows each region to be optimized independently, with the bulk region providing enhanced coupling ratio without requiring additional masking steps across the entire wafer.
Solution Approach 2:
Different quality characteristics are applied to different parts of the device. The bulk region uses n-type well doping for superior coupling ratio, while the SOI region uses p-type well doping for manufacturing efficiency. This local differentiation enables the device to achieve high coupling ratio in critical areas without incurring the full cost of enhanced manufacturing across the entire structure.
2Ease of manufacture
If conventional MTP cell design is used, then manufacturing is simpler, but cell size is large
Solution Approach 1:
The patent transitions from a planar MTP cell design to a three-dimensional structure by forming vertical floating gate stacks that extend through the oxide layer. This vertical dimensionality change allows the cell to achieve higher density and smaller footprint while maintaining manufacturing simplicity through standard semiconductor fabrication processes.
Solution Approach 2:
The floating gate stacks are nested within the hybrid bulk-SOI structure, with the gates vertically positioned over the wells. This nesting arrangement allows multiple functional elements to occupy the same lateral footprint, effectively reducing the cell area while maintaining all necessary manufacturing steps.
3Device complexity
If conventional MTP cell design is used, then structure is simpler, but access time is slow
Solution Approach 1:
The patent changes the electrical parameters of the device by implementing a hybrid bulk-SOI structure with dual well types. The n-type well in the bulk region provides enhanced charge storage capability and faster erase characteristics, while the p-type well in the SOI region maintains acceptable read performance. This parameter optimization achieves faster access time without dramatically increasing structural complexity.
4Reliability
If hybrid bulk-SOI structure is implemented, then performance is enhanced, but device complexity increases
Solution Approach 1:
The device is segmented into functionally distinct bulk and SOI regions, each optimized for specific performance characteristics. The bulk region handles high-performance requirements (coupling ratio and erase speed), while the SOI region handles cost-effective manufacturing and read operations. This segmentation allows performance enhancement without requiring the entire device to be complex.
Solution Approach 2:
The hybrid bulk-SOI structure serves multiple functions simultaneously: the bulk region provides high coupling ratio and fast erase, the SOI region provides manufacturing efficiency and acceptable read performance. This multi-functionality allows the device to achieve enhanced overall performance without proportionally increasing complexity, as each region contributes different capabilities.
Data Source
AI summary
A method of forming a low-cost and compact hybrid SOI and bulk MTP cell and the resulting devices are provided. Embodiments include forming a bulk region in a SOI wafer; forming an NW in the bulk region and a PW in a remaining SOI region of the SOI wafer; forming first and second pairs of common FG stacks over both of the SOI and bulk regions; forming a first shared N+ RSD between each common FG stack of the first and second pairs in a top Si layer; forming a N+ RSD in the top Si layer of the SOI region on an opposite side of each common FG stack from the first shared N+ RSD; forming a second shared N+ RSD between each common FG stack in the bulk region; and forming a P+ RSD between the first and second pairs in the bulk region.