Hybrid SOI Substrate Layout for Memory, Transistor, and Logic Cells
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Solution Overview
Problem
Non-volatile memory devices and transistor devices are not conducive to silicon on insulator (SOI) substrates due to the requirement for deeper source and drain regions than the thickness of the silicon layer, making it difficult to combine the advantages of logic devices formed on SOI substrates with memory and transistor devices formed on bulk substrates.
Innovation Solution
A method of forming a semiconductor device by providing a substrate with bulk silicon, an insulation layer, and a silicon layer, and then performing an etch process to expose the bulk silicon in specific areas while maintaining the insulation and silicon layers in another area. This allows for the formation of memory cells, transistor devices, and logic devices in different areas of the substrate, enabling operation at higher voltages without junction breakdowns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory devices and transistor devices are formed on SOI substrates, then device performance is improved, but deeper source and drain regions cannot be formed due to limited silicon layer thickness
Solution Approach 1:
The substrate is segmented into multiple regions with different structures: a first region with bulk silicon for memory and transistor devices requiring deep source/drain regions, and a second region with SOI structure for logic devices benefiting from reduced parasitic capacitance. This segmentation allows each device type to operate in its optimal structural environment without compromise.
Solution Approach 2:
Different substrate structures are provided in different local regions: bulk silicon in the first region where deep junctions are needed, and thin silicon-on-insulator in the second region where low capacitance is needed. This local differentiation of substrate quality enables simultaneous optimization for different device types in the same integrated circuit.
2Ease of manufacture
If logic devices are formed on bulk substrates, then deeper source and drain regions can be formed, but parasitic device capacitance increases reducing performance
Solution Approach 1:
The substrate is divided into functional zones where logic devices are specifically placed in the second region with SOI structure. This spatial segmentation ensures that logic devices benefit from reduced parasitic capacitance while memory and transistor devices in the first region utilize bulk silicon for deep source/drain formation.
Solution Approach 2:
The substrate provides locally optimized properties: thin silicon layer with insulator in regions where low capacitance is critical for logic devices, and bulk silicon in regions where deep junction formation is critical for memory and transistor devices. Each local region has the quality needed for its specific device type.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the combination of SOI substrate advantages with memory and transistor devices, allowing for higher voltage operation without junction breakdowns, while also simplifying manufacturing and reducing silicon geometries for logic devices.
Implementation Method 1
performing an etch process to remove the silicon layer and the insulation layer from a first area and a second area of the substrate to expose the bulk silicon
Data Source
AI summary
A method of forming a semiconductor device by providing a substrate having bulk silicon, an insulation layer over the bulk silicon, and a silicon layer over the insulation layer. The silicon and insulation layers are removed from first and second areas, while maintained in a third area. A memory cell is formed in the first area having a floating gate over a first portion of a memory cell channel region and a control gate over a second portion of the memory cell channel region. A transistor device is formed in the second area having a transistor gate over a transistor channel region. A logic device is formed in the third area having a logic device gate over a logic device channel region. The memory cell channel region and the transistor channel region are disposed in the bulk silicon. The logic device channel region is disposed in the silicon layer.