Hybrid Solder-Polymer Buffer Layer for Thermo-Mechanical Stress Mitigation
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Solution Overview
Problem
Thermo-mechanical stress-induced defects such as delamination and crack formation at the interface between chip and chip carrier in electronic devices, caused by high temperature or high pressure processes during manufacturing, compromise the reliability and lifetime of these devices.
Innovation Solution
A hybrid connection layer arrangement is introduced, comprising a solder layer covering over 70% of the contact area and a polymer buffer layer covering less than 30%, with the polymer layer being elastic and optimized for thermal expansion to mitigate stress and provide a strong, reliable connection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If high temperature or high pressure processes are applied during device manufacturing and assembly, then strong bonding between chip and carrier is achieved, but thermo-mechanical stress causes delamination and crack formation at the interface
Solution Approach 1:
The patent introduces a buffer layer with specifically engineered mechanical properties (elastic modulus between 1-10 GPa) and thermal expansion coefficient (50-150 ppm/K) to change the parameter set of the connection structure, allowing it to withstand thermal cycling and mechanical stress without delamination or cracking
Solution Approach 2:
The patent creates a composite connection structure consisting of the buffer layer combined with conductive materials (solder, copper, or conductive adhesive). This composite approach integrates both mechanical buffering functions and electrical conduction functions, resolving the contradiction between strong bonding and interface reliability
2Strength
If a rigid connection structure is used to ensure structural stability, then mechanical strength is improved, but stress concentration occurs at the chip-carrier interface under thermal expansion
Solution Approach 1:
The buffer layer's elastic modulus (1-10 GPa) is specifically designed to be lower than both the chip and carrier materials, creating a compliant intermediate layer that absorbs thermal expansion stress and prevents stress concentration at the rigid chip-carrier interface
Solution Approach 2:
The buffer layer's thermal expansion coefficient (50-150 ppm/K) is engineered to bridge the gap between the chip and carrier thermal expansion characteristics, allowing the structure to expand and contract uniformly during thermal cycling without generating excessive stress
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly reduces the occurrence of cracks, fractures, and delaminations, enhancing the reliability and durability of the electronic devices by alleviating stress forces and moderating thermal expansion differences between materials.
Implementation Method 1
the polymer layer being elastic and optimized for thermal expansion to mitigate stress
Implementation Method 2
moderating thermal expansion differences between materials
Data Source
AI summary
An electric device and a method of making an electric device are disclosed. In one embodiment the electric device comprises a component comprising a component contact area and a carrier comprising a carrier contact area. The electric device further comprises a first conductive connection layer connecting the component contact area with the carrier contact area, wherein the first conductive connection layer overlies a first region of the component contact area and a second connection layer connecting the component contact area with the carrier contact area, wherein the second connection layer overlies a second region of the component contact area, and wherein the second connection layer comprises a polymer layer.