Hybrid Solid-State Memory Wear Leveling via Write Frequency Rankings

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Solution Overview

Problem

Flash memory devices have a limited number of write cycles, making them unsuitable for long-term mass storage in computer systems due to rapid degradation, unlike magnetic hard disk storage which has a significantly longer lifespan.

Innovation Solution

A hybrid solid-state memory system is proposed, combining high-write-cycle nonvolatile memories with lower-cost, higher-capacity memories, where frequently changing data is stored in high-write-cycle memories and less frequently accessed data is stored in lower-write-cycle memories, using a fatigue management module to optimize write operations and extend the lifespan of the device.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If flash memory devices are used for mass storage, then storage capacity and cost-effectiveness are improved, but write cycle lifetime is insufficient

Engineering Contradiction:
Improvestorage capacityVSAvoidwrite cycle lifetime
Core Design Contradiction:
Quantity of substanceVSDuration of action of stationary object

Solution Approach 1:

The patent segments the flash memory device into multiple pools of memory blocks, categorizing them by wear level (e.g., lightly worn, moderately worn, heavily worn). This segmentation allows the system to manage different blocks according to their remaining lifespan, directing future writes to healthier blocks while preserving data on degraded blocks, thereby extending the overall device lifetime.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic remapping of logical addresses to physical blocks based on real-time wear status. As blocks degrade, the system dynamically adjusts the mapping to redirect writes to fresher blocks, ensuring optimal utilization of available capacity while maximizing the operational lifetime of the storage device.

Inventive Principle:
Principle #15Dynamics

2Quantity of substance

If multi-level cell flash memory is used to increase capacity, then storage density is improved, but write cycle lifetime is reduced

Engineering Contradiction:
Improvestorage densityVSAvoidwrite cycle lifetime
Core Design Contradiction:
Quantity of substanceVSDuration of action of stationary object

Solution Approach 1:

The patent applies different management strategies to different pools of memory blocks based on their local characteristics (wear level, cell type). SLC blocks with higher endurance are managed differently from MLC blocks with lower endurance, allowing the system to optimize for both density and lifetime by leveraging the strengths of each block type in appropriate contexts.

Inventive Principle:
Principle #3Local quality

3Duration of action of stationary object

If wear leveling is implemented to extend lifetime, then write cycle distribution is improved, but device complexity increases

Engineering Contradiction:
Improvewrite cycle lifetimeVSAvoidcontroller complexity
Core Design Contradiction:
Duration of action of stationary objectVSDevice complexity

Solution Approach 1:

The patent performs preliminary classification of memory blocks into wear-based pools during initialization and ongoing operation. By pre-organizing blocks into manageable pools with similar wear characteristics, the controller simplifies the wear leveling process, as it only needs to manage writes within and between pools rather than individually tracking every block's wear status.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10067866B2Method and apparatus for mapping logical addresses between memories of a solid-state disk based on write frequency rankings
Publication Date: 2018.09.04 MARVELL ASIA PTE LTD
  • US10067866B2 patent drawing
  • US10067866B2 patent drawing
  • US10067866B2 patent drawing

AI summary

A solid-state disk including first and second memories and a wear leveling module. The second memory has a lower write cycle lifetime than the first memory. The wear leveling module: receives logical addresses (LAs) from a host; determines write frequencies respectively for the LAs, where the write frequencies indicate how frequently data is written to the LAs; determines write frequency rankings (WFRs) based on respectively the write frequencies, where each of the WFRs is based on a weighted time-decay average of write counts or an average of elapsed times of write cycles for the corresponding one of the LAs; and for each LA mapped to the first memory, if a corresponding one of the WFRs is greater than a lowest one of the WFRs of (i) the first memory, or (ii) the first and second memories, remaps the LA with the lowest WFR to a different physical address.