Hybrid SOT-STT Memory Cell for Fast, Dense Writing

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Solution Overview

Problem

Existing MTJ-based memory cells struggle to achieve both fast writing operations and high memory density, as SOT-MTJ cells enable faster writing but have lower density, while STT-MTJ cells offer higher density but slower writing.

Innovation Solution

A hybrid SOT-STT memory cell design that incorporates two MTJ layer stacks, one switchable via SOT and the other via STT, utilizing the lateral extension of the SOT layer to accommodate both, allowing for independent switching mechanisms and increased density.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If SOT-based switching is used to enable faster writing operations, then writing speed is improved, but memory density decreases due to increased footprint

Engineering Contradiction:
Improvewriting speedVSAvoidmemory density
Core Design Contradiction:
SpeedVSQuantity of substance

Solution Approach 1:

The memory cell is segmented into two distinct MTJ layer stacks: a first MTJ layer stack switchable via SOT mechanism and a second MTJ layer stack switchable via STT mechanism. This segmentation allows each stack to be optimized for its specific switching method, enabling the cell to achieve both fast writing (via SOT) and high density (via compact STT structure)

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The SOT layer is designed to serve multiple functions: it acts as the switching mechanism for the first MTJ layer stack (enabling fast writing) and simultaneously serves as part of the structural framework that accommodates the second MTJ layer stack. This multi-functionality allows the cell to leverage both SOT and STT mechanisms within a unified structure, achieving both speed and density

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Quantity of substance

If STT-based switching is used to achieve higher memory density, then memory density is improved, but writing speed decreases

Engineering Contradiction:
Improvememory densityVSAvoidwriting speed
Core Design Contradiction:
Quantity of substanceVSSpeed

Solution Approach 1:

The patent merges two previously separate approaches (SOT-MTJ and STT-MTJ) into a single hybrid memory cell structure. The first MTJ layer stack uses SOT switching for fast writing, while the second MTJ layer stack uses STT switching for high density. By combining these two mechanisms in one cell, the invention achieves both fast writing speed and high memory density simultaneously

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The hybrid design enables faster writing speeds and higher memory density by leveraging the advantages of both SOT and STT switching mechanisms, optimizing space utilization and switching efficiency.

Implementation Method 1

writing the MTJ though spin-orbit-torque (SOT) induced switching of the MTJ

Methodology Applied
Scientific EffectSpin-orbit torque (SOT):

Implementation Method 2

the state is switched by passing an 'STT-switching current' in an out-of-plane direction (e.g. bottom-up or top-down) through the MTJ layer stack

Methodology Applied
Scientific EffectSpin-transfer torque (STT):

Implementation Method 3

the orientation of the free layer magnetization is switched relative to a (fixed) reference layer magnetization, e.g. to be oriented along (a 'parallel' state, P) or against the reference layer magnetization (an 'anti-parallel' state, AP)

Methodology Applied
Scientific EffectMagnetoresistance:

Data Source

PatentEP4012710B1A memory cell, device and method for writing to a memory cell
Publication Date: 2025.07.23 INTERUNIVERSITAIR MICRO ELECTRONICS CENT (IMEC VZW)
  • EP4012710B1 patent drawingFigure 1a~1b
  • EP4012710B1 patent drawingFigure 2a~2b
  • EP4012710B1 patent drawingFigure 3

AI summary

According to an aspect there is provided a memory cell (10, 50). The memory cell (10, 50) comprises: a first (21, 61) and a second (22, 62) electrode; a spin-orbit-torque, SOT, layer (30, 70) comprising a first (31, 71) and a second (32, 72) electrode contact portion arranged in contact with the first (21, 61) and the second (22, 62) electrode, respectively, and an intermediate portion (33, 73) between the first and second electrode contact portions (31, 32, 71, 72); a first magnetic tunnel junction, MTJ, layer stack (41, 81) arranged in contact with the intermediate portion (33, 73); and a second MTJ layer stack (42, 82) arranged in contact with the first or second electrode contact portion (32, 72). A memory device (90) comprising such a memory cell (10, 50) and a method (100) for writing to such a memory cell (10, 50) are also provided.