Hybrid Source/Drain Epitaxy for Lower Parasitic Capacitance
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Solution Overview
Problem
As semiconductor technology advances towards smaller technology nodes, multi-gate devices face challenges with parasitic capacitance, particularly in high-speed circuits, which affects the RC response time and circuit performance due to the large volumes of source/drain epitaxial features.
Innovation Solution
The method involves forming multi-gate devices with source/drain epitaxial features of hybrid profiles and volumes in different regions, allowing for varying numbers of active channel layers to suit different applications, reducing parasitic capacitance by optimizing the construction of GAA transistors in high-speed regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If source/drain epitaxial features with large volumes are used in multi-gate devices, then current driving capability is improved, but parasitic capacitance increases and RC response time deteriorates
Solution Approach 1:
The patent applies local quality by creating different epitaxial feature configurations in different regions of the same device. First regions have epitaxial features with first dimensions optimized for current driving capability, while second regions have epitaxial features with second dimensions optimized for reduced parasitic capacitance. This allows each region to have locally optimized properties suited to its specific functional requirements.
Solution Approach 2:
The patent segments the device into multiple functional regions with different epitaxial feature characteristics. By dividing the device structure into first regions and second regions with distinct epitaxial feature dimensions, the patent enables independent optimization of current driving capability and parasitic capacitance reduction in different segments of the same device.
2Reliability
If different fabrication processes are used for different transistor regions to optimize performance, then circuit performance improves, but manufacturing complexity and costs increase
Solution Approach 1:
The patent applies universality by designing a single fabrication process that can produce multiple different epitaxial feature configurations within the same device. The fabrication process is configured to form first epitaxial features in first regions and second epitaxial features in second regions using the same process steps, thereby achieving region-specific optimization without requiring separate fabrication processes for each region.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of transistors with reduced parasitic capacitance, improving circuit performance and efficiency while maintaining similar processes across the chip, thus enhancing yield and reducing costs.
Implementation Method 1
forming a doped epitaxial feature over the undoped layer, the doped epitaxial feature covering terminal ends of the channel layers that are above the bottommost channel layer
Data Source
AI summary
A method includes forming a stack of channel layers and sacrificial layers over a substrate, patterning the stack to form a fin-shape structure, and recessing a portion of the fin-shape structure to form a recess. A top surface of the substrate under the recess is covered at least by a bottommost sacrificial layer of the stack. The method also includes forming inner spacers on terminal ends of the sacrificial layers that are above the bottommost sacrificial layer, depositing an undoped layer in the recess, and forming a doped epitaxial feature over the undoped layer. The undoped layer covers terminal ends of a bottommost channel layer of the stack. The doped epitaxial feature covers terminal ends of the channel layers that are above the bottommost channel layer.