Hybrid Spice IBIS AMI Signal Integrity Simulation
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Solution Overview
Problem
Current simulation methods, such as using a general model to approximate the Spice model, often result in inaccurate signal integrity simulations, especially when the link signal quality is low, and cannot effectively characterize actual link characteristics, particularly when trying to simulate a link with both IBIS AMI and Spice models, leading to unreliable risk assessments.
Innovation Solution
A method is developed to simulate signal integrity by establishing a transient simulation link with a Spice model as the front-end chip and a channel simulation link with IBIS AMI models for the relay and back-end chips, using step response data and random code signals to form an eye pattern, ensuring accurate characterization of signal transmission through the link.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a general model is used to approximate the Spice model for simulating the front-end chip, then channel simulation can be implemented with IBIS AMI models for relay and back-end chips, but simulation accuracy deteriorates especially when link signal quality is small
Solution Approach 1:
The simulation link is divided into three distinct segments: a front-end chip segment using Spice model, a channel segment using IBIS AMI model, and a back-end chip segment using IBIS AMI model. Each segment maintains its original modeling characteristics while being integrated through standardized interfaces, allowing both model types to coexist without approximation.
Solution Approach 2:
A channel model serves as an intermediary between the Spice model front-end chip and the IBIS AMI model back-end chip. This intermediary enables signal transmission and interaction between the two different model types, facilitating hybrid simulation without requiring conversion or approximation of either model.
2Ease of operation
If a general model is used to replace the Spice model, then simulation can be performed, but the simulation result greatly differs from actual link characteristics when link signal quality is small
Solution Approach 1:
Different parts of the simulation link are assigned different modeling qualities appropriate to their function: the front-end chip uses the more accurate Spice model for precise electrical characteristics, while the channel and back-end use IBIS AMI models for their respective strengths, optimizing overall simulation reliability.
Solution Approach 2:
The simulation setup is configured in advance with properly terminated transmission line models and matched impedance configurations, ensuring that the hybrid model accurately represents actual link characteristics before simulation begins, eliminating the need for post-hoc corrections.
3Adaptability or versatility
If the Spice model provided by some manufacturers is special and difficult to be approximated to the general model, then active simulation cannot be performed, but only experience-based risk assessment can be done
Solution Approach 1:
The simulation methodology is designed to be universally applicable to any Spice model from different manufacturers by using standardized channel models and IBIS AMI interfaces. This universal approach enables active simulation for special Spice models without requiring manufacturer-specific approximations or conversions.
Solution Approach 2:
Instead of attempting to approximate or convert special Spice models to general models, the invention creates a virtual copy of the actual link configuration using the original Spice model as provided by the manufacturer, preserving all unique characteristics while enabling simulation through the hybrid architecture.
Data Source
AI summary
A method for simulating signal integrity of a hybrid model is provided, which includes: establishing a transient simulation link including a front-end chip model, a pre-link model and a terminating impedance model, where the front-end chip model is a Spice model; inputting an ideal step signal to a port reserved in the front-end chip model, and extracting step response data in a steady state; inputting the step response data to an input end of a channel simulation link, where the channel simulation link includes a relay chip model, a post-link model and a back-end chip model, and each of the relay chip model and the back-end chip model is an IBIS AMI model; and inputting a random code signal to the input end of the channel simulation link, and reading a signal outputted from an output end of the back-end chip and forming an eye pattern.