Hybrid SRAM Latch Array With Cross-Balanced Multiplexer Rows
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Solution Overview
Problem
8T static random access memory (SRAM) arrays are not scaling well in terms of area in newer technology nodes, and traditional SRAM bit cells face inefficiencies due to contention during write operations and area utilization challenges.
Innovation Solution
Implementing a latch bit cell design with separate read and write ports, using standard cell design rules to reduce area overhead, and incorporating a write mask mechanism to enable efficient write operations by disabling feedback during writes and utilizing different threshold voltages for read and write transistors, along with a hybrid standard cell library to balance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional 6T or 8T bit cells are used in SRAM arrays, then write operations can be performed, but area utilization efficiency deteriorates and contention occurs during write operations
Solution Approach 1:
The bit cell is segmented into separate read and write ports with independent transistor sets. The write port uses transistors optimized for write operations while the read port uses transistors optimized for read operations, eliminating contention and improving area utilization efficiency
Solution Approach 2:
The feedback path is dynamically controlled to be enabled during read operations and disabled during write operations. This dynamic switching eliminates write contention and improves write efficiency while maintaining read functionality
2Productivity
If SRAM arrays are scaled to newer technology nodes, then transistor density increases, but area utilization efficiency deteriorates
Solution Approach 1:
Different threshold voltage transistors are used in different parts of the bit cell. Low threshold voltage transistors are used in the read port for fast read operations, while high threshold voltage transistors are used in the write port and feedback path to reduce leakage and improve area efficiency
Solution Approach 2:
The patent changes the threshold voltage parameter of transistors based on their functional role within the bit cell, optimizing performance for each specific operation while improving overall area utilization
3Area of stationary object
If standard cell design rules are used, then area overhead is reduced, but performance varies between different rows
Solution Approach 1:
The SRAM array is segmented into alternating rows with different performance characteristics. Even rows use high performance standard cells while odd rows use high density standard cells, creating a balanced hybrid architecture
Solution Approach 2:
Different standard cell types are applied to different rows based on their performance requirements. This local differentiation allows the array to achieve both area efficiency and performance consistency through the hybrid configuration
4Speed
If high performance transistors are used throughout, then read speed improves, but leakage current increases
Solution Approach 1:
Low threshold voltage transistors are used only in the read port where fast read speed is critical, while high threshold voltage transistors are used in the write port and feedback path where leakage reduction is more important, achieving both speed and low leakage
Data Source
AI summary
A static random access memory (SRAM) includes fast SRAM bit cells and fast multiplexer circuits that are formed in a first row of fast cells in a hybrid standard cell architecture. Slow SRAM bit cells and slow multiplexer circuits are formed in a second row of slow cells. The slow multiplexer circuits provide a column output for the fast SRAM bit cells and the fast multiplexer circuits provide a column output for the slow SRAM bit cells. Thus, one SRAM column has fast bit cells and slow multiplexer stages while the adjacent SRAM column has slow bit cells and fast multiplexer stages to thereby provide an improved performance balance when reading the SRAM.