Hybrid SRAM Memory Cell With Resistive Non-Volatile Storage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current memory technologies face challenges in achieving fast access speeds and integrating non-volatile data storage while maintaining low endurance and high supply voltage requirements, particularly in volatile SRAM and flash memory.
Innovation Solution
A memory device with resistance switching elements, such as magnetic tunnel junctions or phase change RAM, is integrated into a memory cell structure, allowing for non-volatile data storage using programmable resistive states that persist even after supply voltage removal, enabling quick data transfer to volatile storage nodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If volatile SRAM is used for fast access, then access speed is improved, but data is lost when supply voltage is removed
Solution Approach 1:
The memory cell is segmented into two functional parts: a volatile SRAM latch for fast access and a non-volatile resistance switching element for data retention. The latch circuit (comprising transistors 102-105 and nodes 106-108) handles rapid read/write operations, while the resistance switching element (202, 204) maintains data persistence across power cycles, resolving the contradiction between speed and reliability through functional division
Solution Approach 2:
The resistance switching element acts as an intermediary between the volatile SRAM latch and external storage. It translates between the voltage states of the latch and persistent resistance states, enabling the latch to operate at high speed while the resistance element ensures data retention without requiring the entire system to operate at low speeds
2Reliability
If flash memory is used for non-volatile storage, then data retention is improved, but access speed deteriorates
Solution Approach 1:
The system segments the memory function into a fast volatile latch portion and a non-volatile resistance switching portion. The latch circuit handles all read/write operations at high speed, while only the resistance switching element requires slower programming operations for data retention, eliminating the speed penalty from flash memory across the entire memory operation
Solution Approach 2:
Data is copied between the volatile latch and non-volatile resistance switching element as needed. During read operations, data resides in the fast latch; during write operations, data is programmed into the resistance element. This copying mechanism allows the system to enjoy fast access speeds for most operations while maintaining non-volatile persistence
3Reliability
If flash memory is used for non-volatile storage, then data retention is improved, but supply voltage requirement increases
Solution Approach 1:
The resistance switching element uses parameter changes in resistance (between high and low states) to store data, rather than requiring the high voltage levels needed by flash memory. This allows the memory cell to maintain data retention capabilities while operating at lower supply voltages suitable for standard CMOS technology, reducing energy consumption during normal operation
4Reliability
If flash memory is used for non-volatile storage, then data retention is improved, but integration with CMOS deteriorates
Solution Approach 1:
The resistance switching element is implemented using materials and structures that are homogeneous with standard CMOS fabrication processes. By using CMOS-compatible resistive switching materials and integrating the element directly into the CMOS memory cell structure, the invention achieves seamless integration without requiring separate fabrication lines or complex multi-step processes, making the non-volatile memory manufacturable using existing CMOS technology
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables fast read and write operations comparable to SRAM, with the ability to store non-volatile data efficiently, reducing the need for external data loading and minimizing bit-flip risks during read operations, while maintaining low operational voltages.
Implementation Method 1
a first resistance switching element coupled between said first supply voltage and a first transistor of said first pair of transistors and programmed to have one of first and second resistances
Implementation Method 2
resistance switching elements, such as magnetic tunnel junctions or phase change RAM
Data Source
Figure 1~2
Figure 3~5
Figure 6~7D
AI summary
The invention concerns a memory device comprising at least one memory cell comprising: first and second pairs of cross-coupled transistors; and a first resistance switching element (202) coupled between a first supply voltage (VDD, GND) and a first transistor of said first pair of transistors and programmed to have one of first and second resistances; and control circuitry adapted to store a data value (DNV) at said first and second storage nodes by coupling said first storage node to said second supply voltage (VDD, GND), the data value being determined by the programmed resistance of the first resistance switching element.