Hybrid SSD HDD Controller Architecture Reducing Pin Count
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Solution Overview
Problem
Current hybrid SSD/HDD storage systems face challenges in optimizing performance and cost due to the inclusion of dynamic random access memory (DRAM) in both SSD and HDD controllers, leading to increased pin count and manufacturing costs, as well as latency issues when DRAM is borrowed between components.
Innovation Solution
A hybrid system architecture where the SSD controller includes DRAM to improve performance and reduces the need for DRAM in the HDD controller, allowing the SSD to interface with the host and provide a tunneling interface for the HDD, while the HDD borrows DRAM as needed, optimizing DRAM usage and reducing pin count and costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If DRAM is included in both SSD and HDD controllers, then performance is improved, but pin count and manufacturing costs increase
Solution Approach 1:
The SSD controller is designed to serve multiple functions: it controls the SSD, provides DRAM caching for the SSD, and acts as a tunneling interface for the HDD to access the shared DRAM. This multi-functionality eliminates the need for a separate HDD controller with its own DRAM, reducing pin count while maintaining performance benefits.
Solution Approach 2:
The patent merges the DRAM caching function into the SSD controller rather than having separate DRAM in both controllers. The HDD shares the SSD controller's DRAM resources, combining two previously separate components into a unified architecture that reduces complexity and pin count.
2Device complexity
If DRAM is borrowed between components, then cost is reduced, but latency increases
Solution Approach 1:
The SSD controller acts as an intermediary between the HDD and the shared DRAM. It manages the tunneling interface and coordinates access to the DRAM cache, mediating between the HDD's read/write operations and the DRAM's fast access capabilities to minimize latency while sharing resources.
Solution Approach 2:
The SSD controller pre-loads frequently accessed data into the shared DRAM cache from the HDD, performing preliminary actions before the HDD needs to access that data. This caching strategy reduces latency by having data ready in fast memory when the HDD requests it.
Data Source
AI summary
A system including a packaging substrate and first and second integrated circuits arranged on the packaging substrate. The first integrated circuit includes a dynamic random access memory. The second integrated circuit includes a system-on-chip, which includes a hard disk controller to control a hard disk drive, a solid-state disk controller to control flash memory arranged external to the packaging substrate, and a dynamic random access memory controller to communicate with the dynamic random access memory. The hard disk controller and the solid-state disk controller access the dynamic random access memory via the dynamic random access memory controller. The dynamic random access memory controller is connected to the dynamic random access memory via the packaging substrate.